DEK, Asymtek, JEOL Join APiA
01/01/2003
SAN JOSE, Calif. — The Advanced Packaging and Interconnect Alliance (APiA) has added several new members to its ranks, covering more of the capabilities related to wafer-level and other advanced packaging capabilities. The APiA facilitates techniques, materials and business models that will enable commercially viable next-generation packaging solutions.
DEK adds to APiA's roster its mass imaging systems, which can be used for wafer bumping, grid array population, encapsulation and underfilling.
Neil MacRaild, manager of DEK's semiconductor packaging technologies group, noted, "Our high-accuracy mass imaging techniques raise throughput, yield and flexibility at wafer and substrate levels, and integrate readily into a complete component packaging line."
Asymtek, a supplier of fluid dispensing equipment to many sectors of the electronics industries, also is a new member of APiA.
Alec Babiarz, senior VP at Asymtek, said, "We are excited about becoming a new member and the opportunity to apply our technology in underfills, wafer applied materials and low-k dielectric coatings using traditional needles and jetting technology."
Also joining APiA recently is JEOL USA, a supplier of automated defect review scanning electron microscopes (SEM). This adds new technology to the metrology side of APiA.
The JEOL SEMs provide automated capture and analysis of submicron images of defects. This is an important capability in wafer bumping and can be integrated with other types of inspection tools.
SEMI Data Shows Geographic Trends
SAN JOSE, Calif.
Semiconductor Equipment and Materials International (SEMI) reported that the billings of worldwide semiconductor manufacturing equipment companies totaled $5.7 billion in the third quarter of 2002. The figure is just over 1 percent higher than the same quarter a year ago, but 22 percent more than the billings figure for the second quarter of 2002.
SEMI also reported worldwide equipment orders of $4.96 billion in the third quarter of 2002, which is 43 percent above the same quarter a year ago, but a 26 percent drop from the previous quarter.
One interesting trend highlighted in SEMI's data is the geographic disparity in the results. As shown in the table, Europe, Japan and North America all saw significant drops over the last year, while Korea, Taiwan and the rest of the world (ROW) all had significant growth. The Asian market is seeing a measurable rebound over the time scale of a year, while the more mature markets of Europe, Japan and North America continued their slide.
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The trends show very clearly the movement of business to regions of Asia (apart from Japan) where manufacturing capability is increasing.
SST and AP China to Begin Publishing in February
NASHUA, N.H. — Advanced Packaging Magazine teamed with Solid State Technology Magazine to create Solid State Technology and Advanced Packaging China, the only magazine covering the full range of semiconductor manufacturing technologies in China, the world's fastest growing market.
The magazine, written in simplified mandarin, will publish five times in 2003 beginning in February. It will be distributed at key 2003 trade shows in China and circulated to more than 6,000 engineers and management at key chip manufacturing, design and packaging facilities throughout China.
According to the China Center for Information Industry Development (CCID), China's chip market is predicted to maintain an average growth rate of
20 percent over the next five years, well above the global average.
Solid State Technology and Advanced Packaging China will contain content translated from the U.S. magazines, as well as local editorial content. In addition to the U.S. edition of Advanced Packaging, the magazine is now combined with Solid State Technology in two other editions, one in China and one in Taiwan.
August Technology Enters China
MINNEAPOLIS — August Technology received its first order for a 3Di Series automated wafer and bump inspection system for use in China. The system will be installed at ACE Semiconductor's Shanghai facility as a part of China's first fully functional 200 mm WLCSP process line.
According to Dan Nelson of August, ACE worked with the APiA to make the equipment choice. August Technology's 3Di Series was designed for advanced packaging applications such as WLCSP, and it features high-throughput 100 percent 2- and 3-D inspection and metrology capability.
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August Technology is a founding member of the APiA and an active member of the Die Products Consortium (DPC).
MEPTEC Symposium Highlights Substrate Options and Strategies
By Julia Goldstein
SUNNYVALE, Calif. — MEPTEC's latest one-day technical symposium held here in November covered the hot topic of substrates. Much of the symposium, titled "Package Systems: Substrate Trends and Challenges," focused on organic build-up technology, but several presenters noted that there is still a need for ceramic substrates, particularly for high I/O products.
Hal Lasky of IBM discussed the need for companies to create partnerships to offer a total packaging solution, and Jim Walker of Dataquest agreed that joint ventures and vendor relationships are critical.
Lasky described the two primary focuses as performance-driven packaging in the system and server markets, and form factor-driven packaging in the wireless and consumer markets. He gave projections for wire bond and flip chip trends over the next few years, stating that flip chip is "making its way into the mainstream" and is no longer a niche technology, but that fine-pitch wire bonding will continue to improve as well.
Ball grid array (BGA) packages with 1.0 mm pitch are now being used primarily in high-end products (with Japanese products using 0.65 and 0.5 mm pitch), but Lasky predicted that 35 percent of all BGAs will use 0.5 mm pitch or less by 2006.
Organic build-up technology needs to move toward finer densities with fewer layers, according to both Lasky and Ron Huemoeller of Amkor. In response to an audience question about the cost of metallization at 20 µm line widths, Lasky said that a 1+1 structure with 20 µm metallization actually could be less costly than a 2+2 structure using 30 µm metallization.
Huemoeller discussed standard and specialty substrate technologies available and the need to fill the "technology gap" for the future. He described the state-of-the-art substrate today as having 25 µm line width, 50 µm pitch, 30 µm vias,55 µm pads and a 0.4 mm ball pitch. Work is still needed to be able to manufacture such a substrate in high volume at low cost, and "innovation, not extension" is needed to push the design rules further, according to Huemoeller. Industry trends are away from paste and toward copper for via fill. Laser drilling is predominant and stacked vias improve electrical performance, a point emphasized by Sabran Samsuri of ASE in his discussion of signal integrity issues.
Amitec's high-density build-up FCBGA substrate, which uses a thin low-k dielectric to enable 10 µm lines, was presented by Dror Hurwitz. He described requirements for the 200 to 450 mm diameter organic wafer cores, including designs that produce sufficiently flat wafers and high Tg materials that are compatible with thin film processing. A compliant interposer layer is used between the eight-layer core and the two thin film build-up layers to planarize the core's top layer.
Toyoki Ito described Hitachi's Foil Additive Method (FAM) for producing a PBGA substrate with 20 µm lines, using copper foil and requiring less etching than sputtered lines. Hitachi has patented a Ni/Pd/Au electroless plating process. With electroless gold plating, the bus bars required for electrolytic gold plating can be eliminated, increasing wiring density, but wire bond and solder joint reliability become poor because of diffusion of Ni onto the bonding surface. Addition of Pd as a diffusion barrier between the Ni and Au greatly improves reliability.
ASE Chooses Cadence
SAN JOSE, Calif.— Advanced Semiconductor Engineering Inc. (ASE) established
a new analysis-driven integrated circuit (IC) packaging design flow using advanced package engineer (APE) software from Cadence Design Systems.
The new design flow allows package-level interconnect characterization and signal integrity analysis so that engineers can make tradeoffs among the
silicon, package and board design options. J.J. Lee, ASE's VP of R&D, described the Cadence design environment as "A comprehensive and integrated packaging solution, one that addresses the challenges of high-speed, high-data rate designs."
This relationship between ASE and Cadence supports the Cadence Design Chain Initiative, an effort whose goal is to help companies improve relationships throughout their design chain.
R&D Key to Amkor Rebound
By Jeffrey C. Demmin
In an exclusive interview with Advanced Packaging, Amkor executives described the company's progress and plans for the emerging rebound in the semiconductor packaging and test outsourcing sector.
Most packaging subcontractors have encouraging news to report these days, with business growing after plummeting in 2001. Amkor Technology has seen more growth than some of its competitors, in part because of the extent of its customer base among the integrated device manufacturers (IDM), rather than the fabless and wafer foundry segments. IDMs are the chip manufacturers that can do their own manufacturing but also rely on outsourcing. During the slump, the IDMs needed less total capacity, so they typically slashed assembly outsourcing, which affected Amkor more than some other companies. Now, with chip sales rising again, the IDMs are returning in earnest to Amkor and other packaging subcontractors for assembly and test services.
Amkor's strategy during the slump was to cut costs in nearly every department except R&D. Bruce Freyman, Amkor's executive VP of manufacturing and product operations, told Advanced Packaging that they still spent $36 million on R&D during the last 12 months, and that its R&D staff is about 300 people strong. Freyman also said that 18 out of Amkor's top 20 customers rank Amkor first in technology.
The areas where Amkor's R&D has continued include flip chip, MEMS packaging, memory cards, stacked die, MicroLeadFrame (or QFN) packaging, and system-in-package (SiP) technology. Freyman noted that Amkor was a pioneer in SiP with significant investments several years ago, and it is starting to pay off now in 2002. He said that Amkor packages 20 percent of the world's RF power amplifiers with SiP technology. Moving forward, wireless local area networking (WLAN) and Bluetooth applications will continue to drive SiP developments.
Also at the forefront of packaging technology is chip/package co-design, and Freyman and Amkor Senior VP Eelco Bergman have seen quite a bit of this happening. They told Advanced Packaging that for high-end flip chip design, Amkor works with its customers' chip designers from the very start of the design process. Various tradeoffs between packaging and chip designs can be made to optimize the performance and cost at the system-level.
Bergman said that there have even been cases of the chip designer increasing the die size, when that decreases the substrate cost enough to offset the increased die cost. It is a good sign that the packaging subcontractors can contribute significantly to this progress. As Bergman said, "We are definitely not going to stop R&D. The technology has not slowed down."