Solder Bumping Single Die
12/01/2005
BY TERENCE Q. COLLIER
Although computers and simulation software have accelerated product development, most electronic products eventually reach the traditional developmental stages of prototypes and samples. The designer’s challenge is to optimize cost-to-performance ratios while finding available components and minimizing board real estate.
Many 21st century products have size or performance specifications requiring flip chip assembly. For these, neither 20th century packaged chips nor wire-bonded bare die make satisfactory prototypes. Bumped flip chip die are essential for representative high-density or high-performance prototypes. With board layout and fabrication costing up to $6K for medium-complexity boards, bumped die save cost and help optimize engineering resources.
While bumped die are desirable at design and development, bumped wafers are not. Most bumping processes are limited to full wafers. Cost for bumping an entire wafer can exceed $15K for just the stencils and tooling. Wafer-bumping lead times can add 6 weeks or more to the bumping cycle.
An alternative to bumping die without bumping wafers is single-die bumping. Until recently, gold stud bumping was the only single-die bumping option. Although stud bumping is suitable for prototypes intended for stud-bump production, stud bumps are not thermally, electrically, or mechanically equivalent to common solder bumps. Thus, stud-bumped single die might not represent the performance of the final solder-bumped product. Stud-bump assembly also requires an entirely different manufacturing technique and equipment from solder-bump assembly.
 Figure 1. SEM of a partially bumped flip chip die with SAC alloy. |
Recent developments in solder-sphere technology make it possible to obtain solder-bumped single die. Solder-bumped prototype die more accurately mirror the performance of the eventual production units, and allow for assembly using readily available surface mount technology (SMT) equipment. Solder-bumped die self-align and provide mechanically strong solder joints. A failed die can be quickly removed and replaced.
This new approach for bumping singulated die attaches solder spheres directly to the die bond pad. It accommodates conventional die, MEMS die, and optical components. Sphere geometry is closely controlled prior to placement, yielding good post-reflow coplanarity. Reliability for both low- and high-bump counts is good. The risk of low-k dielectric damage is less than for stud bumping.
Solder bumps are available in various alloys, including indium-based materials and high-lead, lead-free, traditional eutectic tin/lead, and low-temperature alloys suitable for flexible substrates with 150°C processing limits. If high-temperature or low-creep performance is critical, gold-tin, solder-bumped single die are available. Bump sizes range from 10 mils (250 µ and larger) down to 1 to 2 mils (25 to 50 µ), with 5-µ coplanarity post-reflow prior to electrical testing.
In some applications, such as lead-free comparison studies, single-chip solder bumping may also reduce wafer scrap. Solder bumps of various compositions may be placed directly on die taken from the same wafer, rather than processing wafer sub-lots at $2400/wafer. A single wafer provides enough samples to effectively evaluate the alloys and study variability.
Solder-bumped die can also be assembled as stacked die. Bumped die deliver mechanical joint strength that is not always obtainable with wire bonds, without damaging the device. Shear values range from 25 to over 100 g of force for some lead-free bump geometries. Heatsinks can be attached directly to the bumped die to improve thermal performance.
To summarize, solder-bumped single die provide samples that will be representative of the end product and manufacturing process. Solder-bumping single die can give a smaller board footprint, faster time-to-market, fewer design iterations, and improved electrical and mechanical performance at lower cost. Available in lead-free and other alloys, solder-bumped single die deliver the high performance required by many applications.
TERENCE Q. COLLIER may be contacted at CVInc., 1155 E. Collins Blvd., Suite 200, Richardson, TX 75081; 214/557-1568; E-mail: [email protected].