Probe Cards Enable Wafer-level Test
12/01/2005
Reducing Cost of Test
BY JULIA GOLDSTEIN
The semiconductor industry trend toward smaller, denser ICs and larger silicon wafers leads to more complex packaging and test requirements, causing packaging and test to consume a larger fraction of the total product cost. Test is often considered a necessary evil; adding cost without providing visible benefits to the end user. Advances in probe card technologies and approaches for wafer-level testing are important steps to reduce the cost of test.
Probe Card Technologies
Probe cards provide an electromechanical interface between the tester and the device-under-test (DUT). Conventional, cantilever-style probe cards have been around for decades, and are a robust, cost-effective solution for many applications. A ring of probes soldered to a PCB contacts the pads on the DUT at a low angle, providing a horizontal scrubbing action, which removes oxides and makes a good electrical contact. An overdrive in the range of 50 to 100 μm is required to compensate for lack of co-planarity in either the probe tips or the device wafer. A variety of probe tip materials and sizes are available, depending on device requirements.
Vertical probe card technologies contact the DUT vertically rather than horizontally using pins or lithographically defined structures. Applications such as flip chip die and some high-density designs require vertical probe cards because cantilever probes are too difficult to align. The size of the probes on cantilever probe cards can limit high-speed testing capabilities since the inductance of the probe becomes a problem. Vertical probes also produce smaller marks than cantilever probes and minimize the chance of damage to the DUT.
 Vertical-style probe card using membrane technology. |
Several types of vertical probing technologies have been developed. The most common consists of an array of pins that act as compressible beams. Damaged pins can be replaced individually without replacing the entire probe card. Another type consists of lithographically defined contact bumps on a flexible membrane core, providing a stable, low-inductance contact. A different lithographic solution uses MEMS technology to produce miniature springs that contact the DUT with extremely low force and low inductance.
Reducing the Cost of Test
Probe card manufacturers are reducing the cost of test in a variety of ways. Increasing the number of devices that can be tested in parallel is one approach. Various manufacturers report ability to test between 8 and 256 dies in parallel, depending on die size and complexity, and probe card capabilities. Memory die are good candidates for highly parallel testing. But for logic, system-on-chip, and RF devices, it is realistic to test a few die at a time. Testing an entire 300-mm wafer in one touchdown is technologically feasible, and some companies are aiming to do this for memory devices in the near future. Others are concerned that the cost of such a probe card might not make it worth the savings in test time, especially for devices with a limited lifespan. Incorporating built-in self-test (BIST) circuits into the die is one way to test more devices in parallel without increasing probe card cost, but device manufacturers are not always willing to give up real estate on the wafer. As the cost of silicon drops, this option is becoming more attractive and may enable cost-effective, full wafer test.
Increasing probe life and time between cleaning can also result in cost savings. During testing, debris from the bond pads or bumps on the wafer contaminates the probe tips. Minor cleaning can be done on-line, but the probe card must be periodically removed for thorough cleaning-typically after about 50,000 touchdowns-and then recalibrated before testing can resume. Unless the test house has a spare probe card, an expensive option if not fully utilized, this means down-time for the tester. Changes in probe tip materials and geometry can minimize the amount of material that sticks to the probe tips, ultimately reducing the need for cleaning; and in one case, allowing up to 300,000 touchdowns between off-line cleanings. The optimum probe tip material and shape depends on whether the probes are contacting aluminum pads, copper pads, SnPb solder bumps, or lead-free solder bumps on the DUT.
 Cantilever-style probe card. |
Accuracy in the testing process is another cost factor. Problems with co-planarity and alignment can require retesting, increasing test time and cost. Vertical probe cards are not as susceptible to these problems as cantilever probe cards, but are also significantly more expensive.
How much testing can be done at wafer-level, saving the cost of packaging defective dies, but at the expense of more complexity at probe is an important cost-reduction question. At-speed functional testing is commonly done on DRAM products, but is much more difficult for logic dies because of their complexity. The frequent die shrinks demanded by the mobile market for FLASH memory devices require new probe card designs; and more extensive testing means a more costly probe card.
Wafer-level Burn-in
The desire for known good die (KGD), particularly for system-in-package (SiP) applications, drives the demand for wafer-level burn-in (WLBI). One company provides probe cards capable of supporting burn-in for NAND and DDR devices. Others choose not to address burn-in at all; in some cases, because their probe cards are not designed to handle the high temperatures typically seen during burn-in. Cost is an obstacle to widespread adoption of WLBI, because of both capital equipment and test time, but increased parallel testing can mitigate this. In SiP applications where KGD are required, wafer-level burn-in may be necessary to ensure sufficient reliability since there is no opportunity to do burn-in of individual packaged dies. For individually packaged parts, moving toward WLBI would avoid packaging faulty dies and reduce final assembly cycle time. Burn-in at wafer-level should ultimately reduce overall test costs for devices manufactured in sufficient volumes.
 Close-up view of vertical probe tips. |
Some customers are requesting both hot- and cold-temperature testing for KGD, posing yet another challenge for WLBI. The mismatch between thermal-expansion coefficients for various materials that make up a probe card causes problems with such a large temperature range. Condensation can also be an issue when testing at low temperatures. Still, some manufacturers have developed solutions that address the need for hot and cold testing.
 Probe card for wafer-level burn-in. |
null
Reducing Contact Force
Sensitive devices-including flip chip die and those using low-k dielectrics-require special attention to avoid damage during testing by reducing contact forces while still maintaining sufficient contact resistance for all dies on the wafer. On bumped wafers, solder-bump heights can vary from center to edge and need to be taken into consideration. Probe card manufacturers have reduced contact force in their products by improving planarity to enable less overdrive; changing the shape of the probe tip to distribute forces over a larger area; and introducing new probe tip materials. In the case of lithographically defined springs, the technology itself applies an order of magnitude less force than conventional probes.
Conclusions
Wafer-level testing continues to evolve, and advances in probe card development are an important piece. Technologies exist for highly parallel testing and for testing any type of device. Probe card manufacturers continue making advances in testing efficiency and complexity. The expansion of at-speed wafer-level test and burn-in to a larger variety of devices and applications comes down to cost-effectiveness compared to testing of packaged parts.
ACKNOWLEDGEMENTS
The author would like to thank Andrei Berar of Kulicke & Soffa, Niranjan Khasgiwale of FormFactor, Karen Lynch of SV Probe, Bruce McFadden of Cascade Microtech, and Patrick Mui of JEM America for providing information and photographs for this article.
JULIA GOLDSTEIN, Ph.D., Advanced Packaging technical editor, may be contacted by calling 408/376-3987, or e-mailing [email protected].