Lead-free Impact on Wafer Bumping & Wafer-level Packaging
11/01/2005
By Thorsten Teutsch
With the July 2006 date for implementation of the EU’s RoHS and WEEE Directives looming, most, if not all producers of electronic products are studying prospective technologies and looking for potential solutions for assembling products using lead-free solders. This ripple effect is reaching wafer bumping as well. While there is an exemption for high-lead solders used in flip chip applications in place, many customers are looking for lead-free solutions in the case the exemption does not hold. Popular areas for investigation include memory products (e.g., SRAM, DDRAM), wafer-level CSPs including integrated passives and protection devices, and small-die flip chip structures. Unfortunately, the integration of lead-free into FC/CSP applications is a difficult task. This is due primarily to the material properties of lead-free solders. With respect to lead-free solder paste, SnAg4Cu0.5 is most common. However, SnAg3Cu0.5 use is rising due to advantages in solder reflow, wherein the thermal profile is less critical and claims of ownership of the SnAg4Cu0.5 alloy arise.
The stiffness and limited compliance of the alloys that meet the lead-free criteria make the achievement of consistent reliability a matter of greater concern than that of traditional leaded solders, which have a proven track record. For example, memory die, which tend to be large eutectic PbSn assemblies, are qualified already, but getting there with lead-free will be difficult. A higher yield loss after board assembly (before underfill) has been observed already. This is due in part to substrate warpage, which is a product of thermal mismatch between the memory chip and the substrate. Lead-free, with its reduced mechanical compliance, fails earlier. In the case of smaller die geometries, the disadvantage of lead-free vs. eutectic PbSn is less dramatic because the total strain is lower.
It is still possible to obtain a measure of acceptable yield using lead-free in wafer-level CSPs. For example, smaller dies (e.g., less than 5 × 5 mm in size) with 500-mm-pitch bump arrays can be assembled without the use of underfill when using 300-mm solder sphere attach. There are also fully qualified processes for such packages after assembly for small dies with I/O counts of 25 or fewer where the CTE-induced strain is low. As evidence, volume production of 3,000 to 5,000 wafers/month for wafer-level package products for mobile phone and consumer electronics applications is occurring.
While progress and improvements continue with experience, there remain some concerns for lead-free flip chip. After die layout, the most frequently discussed issue relative to lead-free bumping is void density in the reflowed solder bump. Investigations have identified that solder paste is critical. While suppliers are working on making improvements, a direct correlation between void density and overall reliability has not been shown, so the importance remains uncertain.
Beyond the need to comply with the legislated demand for lead-free products, there are limited technical advantages for lead-free solders in wafer-level-bumped products, and a significantly greater number of concerns. On the positive side, the electro-migration properties of lead-free are better. Because of the absence of lead, there is a reduced concern relative to alpha-particle emission. For memory products and high-performance processors, this is an important issue. On the down side, lead-free offers no proven environmental advantage and it may, on the whole, be worse. Narrower process windows for bumping and assembly (reflow, solder wetting, etc.) can lower, and potentially exacerbate reliability expectations. There are also expected higher board-material costs due to higher reflow temperatures combined with higher manufacturing costs due to higher reflow temperature, the need for more advanced flux cleaning and higher material cost, etc.
Summary
To make lead-free interconnect technology a strong alternative to eutectic PbSn, more cooperative interfacing between those involved in wafer design, wafer fabrication, wafer bumping, and die assembly will be necessary. Lacking intrinsic mechanical compliance, lead-free solders for flip chip applications may require use of alternative under-bump strain-relieving technologies; unfortunately, these will drive up cost rather than lower it.
With respect to wafer bumping, two areas related to efforts to reducing void density and improving low-cost solder bumping capabilities to meet the need for lower I/O pitch limits (120 to 150 mm) and higher I/O density (~ 400-k I/Os per wafer) pose challenges. A micro-ball gang-placement process that is in development may provide a solution for both challenges. While there are matters of concern relative to lead-free solder, progress is being made. Moreover, research and development activities in pursuit of viable solutions for lead-free will continue.
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THORSTEN TEUTSCH, president, may be contacted at Pac Tech USA, 328 Martin Avenue, Santa Clara, CA 95050, 408/588-1925; E-mail: [email protected].