Thermally Enhanced, Next-generation 3-D Power Packages
11/01/2005
A Heat-Management Solution
BY BRYAN ONG, S.G. CHOW, AND EDDY TANG
The ability to adequately dissipate heat is a constraint on the complexity of package architecture design, smaller footprint, and higher device operating speed and power consumption. When electrical-power-consumption-per-unit volume for a semiconductor device increases its density, the corresponding heat generated also increases. More and more packages are designed with an external heatsink, or heat slug, to enhance the heat-dissipation capability. New-generation devices’ operating frequency and higher-level large-scale integration (LSI) need back-end semiconductor manufacturing to beef up the heat management capability within an encapsulated package.
Stray and spreading resistance reduction for heat management in power-discrete semiconductor packages - such as voltage regulator modules (VRMs) - is progressing. In this case, SO-8 is used as voltage regulator/converter. The inferior thermal capability of the SO-8 package makes it necessary to parallel multiple devices; spreading the heat generated and preventing any one device from running too hot. Too many devices-in-parallel occupy printed circuit board (PCB) real estate, increasing system-level manufacturing cost, and negatively impacting the VRM overall operating efficiency.
System-level design takes board-level mounting as main measurement criteria towards achieving end-product application miniaturization. Vertical expansion - such as multiple-die stacking or package-on-package (PoP) stack - is one of the ubiquitous solutions in the market. Hot spotting may occur under high temperature in high-current power devices, since electrical current concentrates in areas around the emitter of a bipolar device. Direct die stacking may not be feasible in this case - the only viable option left is PoP.
The current design of lead and lead-free versions of SO-8 has no thermal or electrical connecting terminals on top of the package surface to link the device common source (S), gate (G), or drain (D) when being stacked. Conjoining two existing SO-8s may cause heat-containment swells between the package mold compound interface (case junction); opposing the need to achieve faster device cooling. Packaging design needs a form-factor change to deliver what the latest power devices in the market require.
When compared to DPAK or other derivative packages, electrical resistance of SO-8 assembly-build features is 7.2% higher than DPAK, and 68 to 72% higher than advanced-derivative power packages. An SO-8 package uses gold wire for interconnection rather than ultrasonic bond aluminum wire. Space on a SO-8 package is limited, so wires must be thin and numerous; contributing significantly to die-free package resistance (DFPR). Loop resistance and spreading resistance can be reduced using wireless interconnect. Resistance caused by lead form is eliminated by introducing a lead-free package.
SO-8 footprint has been widely adopted in metal oxide semiconductor field effect transistor (MOSFET) and insulated gate bipolar transistor (IGBT) device packaging over the last few years. MOSFET has existed for several decades, supplanting the bipolar power transistor in power-switching applications, and remains the switching device-of-choice for many applications. MOSFET on-state resistive characteristics allow it to offer lower on-state voltage drop. Clocking speed of MOSFET is much faster than IGBT.
MOSFET die packages require higher heat dissipation capability than small-outline integrated circuit (SOIC) devices that obtain faster switching capability, and reduce the propensity for thermal runaway. Copper-strap bonding, external heatsinking, and flip chip-bumping interconnect packages are among the favorable, recently introduced, drop-in design choices of enhanced SO-8 packages.
Shortcomings on board-level flexibility and design limitations prevent these packages from becoming popular replacements of standard-legacy power products. Direct-chip-attach (DCA) or flip chip-on-board (FCOB) to PCB packages will have footprint-compactibility issues whenever board size shrinks. Board I/O routing customization requires precise alignment of solder balls. Sourcing MOSFETs from different integrated device manufacturers (IDM) pose problems for outsourcing and electronics manufacturing services (EMS) companies. Some DCA chips require proprietary top metallization coating to protect active circuit layout; incurring a higher raw material cost.
Other advanced power packages - such as direct-die backside exposed with copper-strap interconnect - have one heat-dissipation path. The micro-gap between die-to-mold compound interface is subject to moisture ingression. Such packages may only be suitable for enterprise voltage regulator down (EVRD) applications, where heat-transportation-to-package ambient environment from the die top is poor.
A hybrid leadframe package* with dual-side heat-dissipation capability resolves these issues at a lower cost-of-ownership. Designed with seamless integration for matching SO-8 or other smaller footprints, this power package uses a hybrid leadframe to achieve dual-side heat-dissipation capability by strategically aligning the top and bottom leadframes together when assembled.
The top heat-dissipation path is constructed from full hard-copper alloy in a large matrix form. Upset by a protruded metal tool set to form a copper cap, the top leadframe is exposed to ambient air after package encapsulation. The top leadframe is used as D for electrical connection to maintain the current between VDS connection and pinchoff condition where VDS becomes saturated. The top leadframe, or exposed heat slug, acts to dissipate heat generated by power semiconductor chips during the device operating period. The large surface of exposed heat slug assists in spreading heat.
Using the same copper alloy material within an encapsulated package reduces the coefficient of thermal expansion (CTE) mismatch and cost of manufacturing. This approach applies to the top and bottom leadframe of the power package. The bottom leadframe serves as electrical, thermal, and board mounting paths, and is used as S and G for electrical connection. Supply voltage is powered through respective leadframe lead paddles; achieving certain voltage gate-to-source (VGS) magnitude. The S and G lead paddles are individually separated. Lead paddles are connected by bottom, half-etch dambars to hold them in matrix-form leadframe.
Designated lead paddles for S and G are always arranged in an opposite direction to facilitate the occupancy of lead paddle in balance condition. Lead paddle maintains a 3:1 ratio for S connection vs. G connection.
Recesses are made approximately the same size as solder-ball or pillar-bump interconnects to facilitate bonding on the bottom leadframe lead paddles. These dimples are 2 to 4 mil in depth - semi-hemispheric for solder balls, and flat for pillar bumps. The dimples, or recesses, are pre-plated with organic, solderable material to enhance solder-on-pad (SOP) flip chip bonding. This design enhances interconnection robustness; reduces DFPR to 0.16 mΩ compared to 1.54 mΩ for the standard SO-8; and approximately 0.4 to 0.8 mΩ for other enhanced type SO-8.
Attachment of the top leadframe is achieved via a mass solder-paste-printing die attach process. The top leadframe is pre-cut according to each mold cup size to ease transportation and make room for optical pad centering (OPC) alignment. A fully assembled bottom leadframe requires three to four pieces of top leadframe, depending on the bottom leadframe strip size. A second pass of solder reflow forms a permanent solder joint. Completed die attach strips are sent for package encapsulation.
 Figure 1 (a&b). Hybrid leadless package and 3-D power package design architectures. |
The package architecture form factor (Figure 1) shows that an encapsulated unit has top and bottom metal exposure, ensuring the package has a dual-side cooling effect for high-current power MOSFET or IGBT devices. This design provides a solution for next-generation bulk converters needing a fast transient response; such as high-end microprocessors running at escalating frequency of 2.0 to 2.5 GHz, exceeding current requirements of 100 A and above (25 A/phase).
A comparison study using computational fluid dynamics (CFD) analysis was conducted to analyze the package theta JA (TJA) performance; gauging hybrid leadframe as a solution for better thermal performance. A 4-layer JEDEC thermal board (76.2 × 114.3 × 1.6mm3), with four I/O pads located at the package corners assigned as common D terminals, was designed - as compared to the industry-standard SO-8 layout. A well-distributed terminals layout is a gain because D is the most efficient heat-dissipating channel. Measurement of heat flow - generated by the power-die-from-package junction to its ambient environment - is conducted in a JEDEC still-air chamber, with typical trace thickness and fan-out trace position centered in the region of 76.2 × 76.2 mm2. Given the power rating of 1 W from silicon die, TJA obtained is 34.27°C/W. This is a remarkable 111.9% improvement over a standard SO-8 package using a power MOSFET die of 2.0x3.0mm23.
 Figure 2. Thermal plot of hybrid package vs. SO-8 under natural heat convection flow. |
Under natural convection of heat flow, this type of hybrid leadframe package has less heat concentration on package die tops compared to the lead-form SO-8. Heat generated from die has greater flow efficiency through the top-exposed heat slug; outperforming SO-8 at 70.4% with a similar bill of materials (BOM) and testing conditions (Figure 2). A study on total exposed area of the top heat slug was also conducted to identify space needed for housing the largest die in the hybrid leadframe package architecture. A maximum exposed area of 6.0 × 3.0 mm2 is the optimal size to compensate four supporting apertures extended to the package bottom plane; each having a dimension of 1.125 × 1.0mm2.
The hybrid leadframe power package outshines the derivative version of SO-8 with the industry’s lowest junction-to-case (RTj-c) and junction-to-air (RTj-a) (Figure 3).
 Figure 3. Comparison of thermal resistance (junction-to-case and junction-to-air) of various SO-8-alike power packages in the market. |
Board-level mounting flexibility, with the ability to alter the bottom leadframe I/O terminals according to each customer’s device I/O layout, makes this design distinctive from others. Chip makers don’t require die-top proprietary passivation, simplifying upstream foundry processes for a wider industry acceptance.
Stacked Packages
A 3-D power package*, using the same hybrid leadframe integration concept, demonstrates a new perspective of package design mobility by using the vertical space available on the package top. This 2-package stack yielded a 50% real estate saving on system-board-level space consumption.
 Figure 4. 3-D power package with standard die layout (same dies) stack option. |
The stack power package comes with two packaging options in regards to die orientation. Standard die layout employs the direct package stacking method. Quad-flat-no-lead (QFN) packages (Figure 4) are preferred for this same die stack. For older surface mount boards requiring package gull-wing lead form, mirror-die layout package stacking is used, requiring IDMs to supply two different die design layouts with mirror reflection.
Thermal performance of the stack power package is as efficient as a single-die hybrid leadframe power package. Faster clock speed under increasing current carrying capacity resulted in a two-combined direct stack option registering TJA at 32.17°C/W; a slight improvement of 6.5% over its single die option. Putting two hybrid leadframe power packages together renders twice the amount of copper heat-slug material in the stack package; accelerating the heat-dissipation capability of two operating power dies. The interface between two stacked packages, separated by a thin layer of selective solder paste, served as stand-off height to achieve a 2-mil gap for heat perturbation.
 Figure 5. 3-D power package junction-to-case highest temperature recorded at 89.33°C, far below the thermal runaway guardband at 125°C. |
Two devices being powered ON-state concurrently caused a higher degree of heat formation in the two-stack power package (Figure 5). Using power supply of 1.0 W, the junction temperature of the top and bottom dies recorded at 89.33°C and 88.39°C, respectively. The combined-die junction temperature did not yield as much as two combined single-die hybrid leadframe power package original junction temperature. However, both temperatures are lower than the generic, single-die SO-8 package temperature of 97.64°C; and the guardband thermal runaway limit of 125°C.
Using two different leadframe designs to achieve dual-side heat dissipation paths for a standard leadframe-base package is not a myth in the industry. Although they withhold some heat generated from the power die, encapsulated packages are still the preferred choice for power semiconductor packages due to mechanical robustness. What really matters is how to integrate the design seamlessly to fit the standard SO-8 footprint using conventional manufacturing methods at a lower cost-of-ownership.
*PowerTOP™
*PowerSTACK™
BRYAN ONG, senior marketing engineer, and CHOW SENG GUAN, member of technical staff, may be contacted at STATS ChipPAC Ltd., 10 Ang Mo Kio St. 65, Techpoint #05-17/20, Singapore 569059; 65/6824-7777; [email protected] and [email protected]. EDDY TANG served as senior marketing manager at STATS ChipPAC, and may be contacted at [email protected].