In the News
03/01/2005
SiP Symposium: Co-design is Key for Miniaturization
SAN JOSE, Calif. - At the 1st Annual SiP Technology Symposium, held Jan. 18, in Tokyo, Japan, co-sponsored by Semiconductor International Japan and Tessera, executives from the U.S. and Japan shared their perspectives on achieving greater electronics miniaturization and performance through advanced electronics packaging. Speakers from Elpida, Hitachi Cable, IBM, Spansion, and others explored how to leverage SiP and other technologies to meet the product and business challenges.
Tessera CFO David Tuckerman kicked off the event with a keynote address on lowering the risk of SiP implementation.
Henry Utsunomiya, Interconnection Technologies president, provided an overview of market trends and applications for multiple-die packaging and echoed the key themes of the event, calling for enhanced cooperation between electronic product manufacturers, semiconductor manufacturers, and materials suppliers to support the development of next-generation electronic products.
Craig Mitchell, Tessera’s VP of marketing, presented a new design methodology, referred to as SLIM, for system-level integration and miniaturization. SLIM-designed systems eliminate unnecessary levels of interconnect and take advantage of the packaging and interconnect technologies currently available to achieve significant size reductions, all while enhancing product performance.
3-D design tools and advanced substrates were identified as key building blocks of SiP systems throughout the symposium. Gordon Jensen, president of CAD Design Software, introduced a 3-D design tool with a manufacturing feedback system that allows complex 3-D packages to be readily designed and optimized for volume manufacturing. Kimit aka Endo, manager of the R&D division at North, discussed North’s copper-bump interconnect technology, which can be used to create high-density, multi-layer substrates.
Ichiro Anjo, Elpida Memory’s senior manager, production engineering department, commented that as DRAM chips move toward higher speeds, they will need to be packaged in FBGAs. With this shift, new stacking technology will also be required to meet the increasing demand in next-generation products.
IBM design engineer, Jonathan Hinkle, discussed the need for advanced packaging in blade-server applications to meet high-density memory requirements. One such example involves the combination of package-stacking technology in a new format memory module called a very-low-profile (VLP) DIMM.
Joseph Fjelstad, co-founder of Silicon Pipe, reviewed the topic of emerging trends in advanced IC packaging and interconnection for high-speed applications. He explored a copper-based interconnect technology designed to close the 10x interconnect gap between signal speeds on ICs and PC boards.
Honeywell Opens Manufacturing Facility in Arizona
MORRIS TOWNSHIP, N.J. - Honeywell’s Specialty Materials business has opened a 40,000-sq.-ft. manufacturing facility in Chandler, Ariz., enhancing Honeywell’s capabilities to supply straight and advanced, customized electronic chemicals. With the opening, Honeywell now operates three of the newest electronic materials facilities in the U.S., including its two other facilities in Bryan and Mansfield, Texas.
The new facility will increase Honeywell’s ability to manufacture application-specific wet-etch and cleaning chemistries. Among their new offerings are wafer-thinning materials that thin the wafer substrate on which chips are built, helping to dissipate the heat produced by high-powered semiconductors.
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The opening follows Honeywell’s November 2004 acquisition of Mitsubishi’s 40% stake in GEM Microelectronic Materials, which gave Honeywell sole ownership of the venture. Construction of the Arizona facility had been started as part of the joint venture. Also in 2004, Electronic Materials acquired a product line and manufacturing facility in Thailand that expanded their capabilities in chip packaging, specifically in the area of thermal management.
Silicon Wafer Shipments Experience Double-digit Growth
SAN JOSE, CALIF. - Worldwide silicon wafer area shipments increased 22% in 2004 over 2003 area shipments, according to the SEMI Silicon Manufacturers Group (SMG). Revenues also grew 26% in 2004, compared to 2003. Shipments in 2004 totaled 6,262 million sq. in. (MSI), up from 5,149 MSI shipped during 2003. Revenues reached $7.3 billion in 2004, up from $5.8 billion posted in 2003. Q4 silicon area shipments declined 9% from the prior quarter, but were up 7% from 2003.
Wafer shipments were over 15% of the total shipments by Q4, and total wafer shipments surpassed the 2000 peak - total revenues in 2004 for silicon wafers fell below the 2000 level. As a result, wafer manufacturers remain cautious investing in new production capacity.
-Lee Mather