That’s How It Stacks up
03/01/2006
Throughout the electronics community, the accepted assumption is that packaging will save the industry. Even package developers anticipate that they can assure higher performance by improving packaging density at a controlled cost. Considering the small size of new devices - iPod Nano, MP4, RAZR, Palm, Blackberry - this requires creativity on the part of packaging engineers with the problems of crosstalk, temperature control, and the demands of fine pitch.
On page 32 of this issue, and in a recent Web-based seminar, Surface Technology Systems’ engineers discussed a device-stacking method for MEMS using deep reactive ion etching of silicon (Si DRIE). DRIE tools can etch deep silicon structures with aspect ratios exceeding 50, selectivity-to-photoresist ratios exceeding 100:1, and etch-depth uniformity better than ±3%, according to this article. Typically wire bonds connect die, but we are approaching limits in interconnect density around the periphery of devices. This method suggests using through-wafer vias with conductive plugs as the interconnections between die.
At a recent Surface Mount Technology Association (SMTA) conference, the Pan-Pacific Microelectronics Symposium, held January 17th on the Big Island of Hawaii, an entire session was dedicated to 3-D integration. Presenter David Scheid of Honeywell discussed a method for vertically integrating thin chips using a seamless, fine-pitch, build-up process to contact bare die directly. The process was designed so that vias can be located anywhere to eliminate the I/O bottleneck at the chip interface. The flexible process enables logic and memory die to be combined to produce a 3-D system-in-package (SiP) solution.
Stacking is not the only way to achieve integration, of course. Professor Rao Tummala of the Packaging Research Center at the Georgia Institute of Technology gave the keynote at the symposium, titled “Nano SoP for Ultra-miniaturized Electronic and Bio-electronic Systems.” System-on-package (SoP) is a system-centric technology based on embedded thin-film components in organic boards or packages. Tummala’s view is that nanopackaging provides embedded functions with thin-film functional components and nanointerconnections in organic boards or packages. In conjunction with SiP modules, nano IC devices, embedded power sources, and user interfaces, SoP also leads to multi-functional systems in the short-term and mega-functional systems in the long run. In other words, the SoP super-package migration to nanoscale (see Advanced Packaging, July 2005) can lead to the integration of the bio-wireless-computing systems, including active and passive components in a single package. This reduces size and interconnect loss due to the embedded nature. It also affords end products such as bio-implanted devices that can sense, digitize, diagnose, monitor, and dispense medicine as needed.
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Can packaging lead the way? In many formats, packaging is all that it’s stacked up to be.
Gail Flower
Editor-in-Chief