NEW PRODUCTS
03/01/2006
Wafer Handling
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Both 200- and 300-mm wafer-handling systems, the EWL-700 line-loading and EWU-700 line-unloading are single cassette handling systems that comply with 10-K cleanrooms. Wafers safely transport from and into Fluoroware or other types of magazine cassettes within a small footprint. PRO-MATION Inc., Kenosha, WI, www.pro-mation-inc.com.
Silicon-based Hermetic Package
The HyCap S QFN/SON hermetic MEMS and IC package conforms to standard QFN/SON package specifications for high-volume SiP applications. Its silicon encapsulation technology enables manufacturers to integrate MEMS with electronic components and passives into one compact package, and matches the CTE of MEMS and CMOS devices. It enables high hermeticity and vacuum levels, coupled with electrical connectivity, through the use of patented microvias that pass from the inside of the cap to surface mount pads on the outside. HyCap attaches to the device to be packaged by metal solder, forming a hermetic seal and electrical contact. A deep cavity allows for additional discrete MEMS or ICs to be integrated with ultra-short electrical connections using either die attach with wire bonding or flip chip technology. Hymite A/S, Kgs. Lyngby, Denmark, www.hymite.com.
CSP Solution
The Flip-Stack CSP targets devices using advanced IC fab processes, mixing a proprietary flip chip process with conventional wire-bond technology to offer a cost-effective, high-performance 3-D package solution. Flip-Stack enables high levels of silicon integration and device performance by stacking flash or mobile DRAM memory over high-performance logic chips, such as DSPs and ASICs. The bottom logic device is attached to the package substrate using lead-free flip chip solder bumps, and the top ICs are then attached to the flip chip die and wire-bonded to the package substrate. Offered in a standard FBGA package outline, Flip-Stack offers a flip chip interconnect that addresses the growing need for improved electrical performance in consumer products containing high-performance components, such as baseband processors and RF ICs. For high-pin-count devices, Flip-Stack’s flip chip architecture reduces wiring complexity. The platform also supports the integration of passive devices within the package to enable total system-in-package (SiP) functionality. Amkor Technology, Chandler, AZ, www.amkor.com.
EDA Software
RioMagic electronic design automation (EDA) software takes package escape, routability, and parasitics into consideration, and enables simultaneous tradeoffs between chip and package design. Employing an interconnect synthesis approach, RioMagic analyzes many variables to converge on a final I/O plan. With its embedded chip/package extraction, estimation, and simulation capabilities for signal and power integrity, the impact on electrical performance is understood and addressed before final implementation. As the design progresses, RioMagic can be used when there are changes in the chip or package design to validate the initial strategy or to re-optimize the I/O plan with the new and updated set of design criteria. Extraction and analysis capabilities approximate signal performance from driver to package ball. On-chip parasitics are extracted using pre-generated look-up tables, while resistance-inductance-capacitance (RLC) models are used to calculate RLC package parasitics early in the process for timing and noise analysis. Rio Design Automation Inc., Santa Clara, CA, www.rio-da.com.
Ceramic Transistor Outlines
These ceramic transistor outlines (CerTOs) are made of ceramics with glass and Kovar housings, and include conductor paths made of tungsten printed into fine layers of unsintered ceramic, allowing for various conductor designs and flexible application. They suit data transmission rates of 10 GBps, particularly in edge-emitting lasers, and offer high thermal resistance, preventing excessive heat build-up and eliminating the need for additional cooling mechanisms. Additional applications include IR technology, and work in conjunction with the “TO-Plus” product line for transmitting data with VCSELs. SCHOTT North America Inc., Elmsford, NY, www.us.schott.com.
Aqueous Conformal Coating
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Aquacoat Plus is a water-based conformal coating specifically formulated for protecting electronic circuitry by coupling physical and electrical properties, eliminating the need for extraction and other precautions. Non-flammable and containing low levels of VOCs, it is phenol-free, and contains no isocyanates, so it can be soldered through without fear of highly toxic gases being produced. Based on polymeric materials, Aquacoat Plus is available in two formulations: WBP is the standard product, while the sprayable WBPS is formulated for use in selective film coating equipment. Electrolube, a division of H K Wentworth Limited, Derbyshire, England, www.electrolube.com.
In-line Transport Platform
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The VPX In-Line Transport Platforms allows up to 3 process chambers to share a low-cost, common wafer transport system. It is designed specifically for the pilot production of devices requiring advanced plasma etch and deposition systems. VPX couples to any of the STS suite of advanced process modules to meet different business models and changes in wafer capacity. The VPX offers the same benefits as the CPX volume cluster platform at lower costs and specifications to meet niche production requirements. Features include the Brooks Marathon Express MX 400 automation platform, single vacuum cassette with wafer mapping, and non-contact optical in-line wafer alignment. Surface Technology Systems plc, Newport, Wales, www.stssystems.com.
LGA/BGA Sockets
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This BGA/LGA family of sockets in a 2.5 × 2.5-in. footprint accommodates devices up to 50 mm2. RC SpringProbe technology provides up to 24 GHz at <-1 dB, consistent resistance, and low normal force of 20 to 45 g/node. Features include an all-metal wire form, replaceable contacts and elements, a vacuum fixture for repopulating supplied RC SpringProbes, and a micro-adjustable, screw-type manual actuator. Additional specifications include <50 mΩ DC resistance and a 100-K minimum cycle life. A contact-element system allows for a wide variety of tip geometries for ball/pin or pad contact requirements. Test height of this interposer design is shorter than 2.54 mm in 1- and 1.27-mm pitch configurations. Ardent Concepts Inc., Hampton Beach, NH, www.ardentconcepts.com.
Test Solution
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The 93000 High-Speed Memory (HSM) Series is a high-volume-production, final-test solution for high-speed DRAM devices. It tests memory device interfaces at speeds exceeding 3.6 Gbps with its tester-per-pin architecture. An integrated test cell ensures reliable operation and high uptime. The test solution supports parallelism of 16× sites for 16× organized extreme-data-rate (XDR) and 32× organized graphics-double-data-rate (GDDR) DRAMs in a single test head without additional hardware costs. It also supports complex test patterns with its non-interleaved, at-speed per-pin algorithmic pattern generator (APG) to ensure required test quality and fast yield learning. The new memory-test language (MTL) allows users to program with test programs in a C++ style for fast test-program generation. Agilent Technologies, Loveland, CO, www.agilent.com.