Satisfying the Appetite of Power-hungry Chips
03/01/2007
BY JAMIE METCALFE and GREG FITZGERALD, Optimal Corp.
Increasing complexity of chips - more transistors operating faster at lower and varied voltages with more I/O - is a well-known phenomenon. At the same time, engineers are pushing the envelope to minimize costs when it comes to leadframe vs. BGA, wire bond vs. flip chip, and organic vs. ceramic substrate.
Signal integrity (SI) issues and tools have come a long way. While there are still problems to be solved, such as high-order multi-gigabit serial interface design, it should no longer be assumed that we are working with ideal power and ground distribution systems (PDS). The goal of a well-designed PDS is stable and clean power to the chips within the required min/max voltage levels for each supply. Simultaneous switching noise (SSN) due to ground bounce on the PDS can lead to false I/O switching. DC and frequency-dependent IR drop on the package and PCB can starve a chip of the necessary voltage to operate correctly.
 Figure 1. Impedance with and without package model. |
The black-box approach to PDS design - where chip, package, and PCB are designed in isolation - is alive and kicking, but that should not be regarded as a good thing. Chip engineers often assume ideal voltage sources to represent the outside world when they analyze IR drop in the chip. Figure 1 compares this ideal with reality.
Similarly, package engineers assume ideal voltage sources at the PCB interface. Figure 2 paints a more revealing picture based on a simple chip/package/PCB combination. With this approach, problems that could be avoided are being thrown over the wall from chip, to package, to PCB engineer.
 Figure 2. Impedance of package and PCB, standalone and combined. |
From a packaging engineer’s perspective, the package by itself is not the biggest problem. Package engineers can add a lot of value in a successful PDS design. They could help the chip engineers by providing PDS models representing more realistic boundary conditions. Additionally, working with the chip engineers, they can provide guidance to the PCB engineers about decoupling strategy.
 Figure 3. Unified package and PCB geometry. |
Chip engineers use power-analysis tools to understand static DC and dynamic IR drop inside the chip, but all too often they are set up with ideal voltage sources at the power bumps. These tools are capable of accepting more complex SPICE models that describe the electrical behavior of the package and PCB. Once the package/PCB model exists, the challenge is how to stitch it into the IC power analysis circuit. Chip engineers often have different net names for the chip’s I/Os, and view the physical design from the top metal layer. Package engineers view the die through the back if it is flip chip, and may have different origin coordinates and die rotation. EDA vendors are working together to agree upon protocols that allow the die pads’ locations and power nets to be automatically mapped when exchanging models. With the push of a button, the package engineer can produce an electrical package model so chip engineers can run their power analysis with realistic boundary conditions.
When it comes to the PCB, the package engineer has to deal with various scenarios: PCB is designed in-house or by the customer. If it is designed by the customer, then more than likely, the layout will not be available and a reference PCB will be designed in-house and used to provide design guidelines and example PCB layout. Either way, the package engineer needs to collaborate with a PCB engineer to develop a clean and accurate PDS.
Key to this collaboration between package/PCB and chip/package/PCB is the ability to create a unified package and PCB model that will capture the complex interactions in the PDS. Figure 3 shows a unified geometry of package and PCB.From here, it is possible to perform an analysis that captures all interactions between package and PCB.
 Figure 4. Chip/package/PCB power integrity co-design flow. |
With this capability, the black-box approach can be enhanced to support a power integrity co-design flow (Figure 4). The first step is to unify the geometry of the package and PCB so that all downstream analyses are applied to the combination. It is common for the package and PCB to be designed using different tools, which may be supplied by different EDA vendors. A single EDA vendor flow cannot solve this problem today; the data standards do not exist in a supportable form. There are “neutral” vendors that can pull this together.
Next, DC IR drop analysis of the package/PCB is performed to examine the voltage regulator module (VRM) setup, IR drop from VRM to the package pins, current density hot spots, and cool spots. From this analysis we can create a resistive network model that can be plugged into the chip-level DC IR drop analysis. If problems are discovered, component placement might be adjusted, more metal and vias might be added, or the stackup might be modified and iterated until the DC IR drop across chip and package/PCB is satisfied.
The next major step concerns AC power analysis (or dynamic IR drop analysis). After deciding upon a target PDS impedance and frequency of interest, engineers analyze the package/PCB for resonances and select a decoupling strategy. This involves designing stack-ups of package and PCB, and identifying capacitor values and placement locations. The capacitor placement locations may affect the package footprint, ensuring that high-frequency bypass capacitors can be placed inside the footprint as close to the chip as possible. Bypass capacitors could also be placed in the package, if cost appropriate.
To do an AC or dynamic IR analysis at the package/PCB level, chip power models describing current signatures at the chip’s bumps are necessary. Simultaneously, an RLC model of the package/PCB PDS must be provided to the chip engineer for dynamic IR analysis of the chip, SSN, and core power analysis. This creates a chicken-and-egg situation; problems found on the chip side may be addressed by modifying decoupling on the package/PCB side and vice versa. This situation should be addressed through the necessary iterations of this AC-analysis loop.
Having a unified model of the chip/package/PCB allows more flexibility in determining where to add decoupling or use other noise-mitigation techniques and eliminates the time and cost penalty of multiple design iterations associated with ‘over-the-wall’ design flows. The end-result of this chip/package/PCB co-design flow will be an optimized PDS: optimized for cost because decoupling capacitors are only used when needed; optimized for performance because the power delivery is clean, stable, and accurate.
For good PDS design, IC suppliers must provide guidelines in the form of application notes and sometimes a reference design. Often, the quality and usefulness of these materials vary widely, and in the poorer cases it is up to the customer to figure it out, with whatever support they can extract from their supplier. In these cases, design schedules are extending and products are failing in the field due to power-integrity problems. When considering power integrity, the IC supplier needs to approach this as a system problem - not only a chip-design problem. IC suppliers are adopting this type of power integrity co-design flow, working together with the EDA vendors of chip, package, and PCB design tools.
JAMIE METCALFE, V.P. business development; and GREG FITZGERALD, director of corporate applications, may be contacted at Optimal Corp., 3 Meeting House Road, Suite 30, Chelmsford, MA 01824; 978/367-0222; E-mail: [email protected] and [email protected].