Compact All-optical Buffers on a Silicon Chip



The use of light signals to connect different chips within a computer or different parts within a chip has attracted lots of attention due to the huge bandwidth provided by optics. In such interconnect networks, buffering light signals is important because optical-to-electrical (O-E) and electrical-to-optical (E-O) conversions can be avoided in network switching nodes. Buffering light is simple as long as the footprint of the buffering device is not limited. By passing light through a long fiber, large buffering capacity can be readily achieved. However, such a straightforward approach is not compatible with applications within a chip or computer. The device footprint of a realistic light buffer should be comparable or even smaller than the electronic circuits. In addition, the fabrication process should be compatible with that of standard CMOS circuits.

Figure 1. Resonators cascaded in APF configuration (false color).
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Previously, light buffers have been demonstrated in silica and Hydex material systems. Due to a relatively small index contrast in these material systems, the waveguide can not be bent with a small bending radius. Therefore, the footprints are in mm-cm2 ranges, which is acceptable for a discrete device. However, for optical interconnects between chips or within a chip, it is still too large, since a light buffer is only one type of functional photonic device required for optical interconnects.

Instead, sub-micron silicon waveguide on silicon-on-insulator (SOI) substrate provides tight light confinement in optical communication wavelength ranges. Light can be re-directed using bends with a few microns of radius, and trapped in resonators; the optical delay can be enhanced, further reducing the footprint. Compact ring resonators can be formed using a submicron silicon waveguide with a few microns of radius. Although a large delay can be achieved using a single high-quality factor resonator, operational bandwidth will be limited. Therefore, designing a light-buffering device by cascading multiple resonators with moderate quality factors simultaneously optimizes the device footprint and bandwidth. Two different types of buffers are demonstrated by cascading ring resonators with 6-µm radius in a coupled resonator optical waveguide (CROW) and all-pass filter (APF) configurations (Figure 1).

Buffering experiments are performed using these two types of devices by measuring the delay in terms of bits at different bit rates. The light is modulated with pseudo-random bit stream (PRBS). The reference optical signal is determined by passing the modulated light through the buffering device while tuning the carrier wavelength out of the resonance. In this case, the light has negligible interaction with resonators, so the delay is negligible. When the carrier wavelength is tuned exactly on resonance, the light has maximum interaction with resonators and as a result, the largest delay can be obtained. A buffering device containing 56 cascaded resonators in APF configuration, achieves a total delay of 510ps, and works up to a bit rate as high as 20Gbits, realizing a total buffering capacity of 10 bits. The device footprint in Figure 1 is as small as 0.03 mm2, making such a device suitable for on-chip applications. In addition, buffering devices containing 100 cascaded resonators in CROW configuration, with a total delay of 220ps, is also demonstrated. Previously, devices with only up to 12 cascaded resonators were reported. Using sophisticated electronic CMOS fabrication tools and highly optimized designs and processes, device parameters can be controlled within a few nanometers’ range, resulting in working photonic devices with up to 100 cascaded resonators.

For practical network applications, buffering of hundreds of bits is needed. This demonstration represents a major step towards this goal, but there is still a long way to go. Currently the capacity is limited by relatively large 20dB losses that are accumulated in multiple resonators. We plan to decrease the loss numbers even further. We are working on two major directions to improve the performance of the buffering device. First is to further increase the buffering capacity. Second is to introduce tunability into the buffering device. This would allow us to actively tune the buffering according to networking requirement.


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FENGNIAN XIA, LIDIJA SEKARIC, AND YURII VLASOV, research staff, may be contacted at IBM’s Thomas J. Watson Research Center, Yorktown Heights, NY 10598; 914/945-2703; E-mail: [email protected].