IMEC Research Energetically Stacks Up
11/01/2008
LEUVEN, Belgium–IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits. In 3D stacked packages, IMEC has announced notable achievements.
In October, IMEC engineers demonstrated the first functional 3D integrated circuits (3D-ICs) made by die-to-die stacking using 5µm Cu through-silicon vias (TSVs). Die stacking was done using 200mm wafers in IMEC’s reference 0.13µm CMOS process with added on Cu TSV steps. Before stacking, the top die was thinned to 25µm and bonded to the landing die using Cu-Cu thermocompression. The next stage is to migrate the process to a 300mm platform.
Tests confirmed that circuit performance does not degrade by adding Cu TSVs to interconnect the layers. To evaluate the impact of the 3D-SIC flow on the characteristics of the stacked layers, both top and landing wafers contained CMOS circuits. To see how the stacked 3D layers performed, ring oscillators with varying configurations were distributed over the two-chip layers and connected to the Cu TSVs. These circuits were tested after the TSV stacking process to confirm that the signal does not degrade by the addition of copper TSVs , and these circuits demonstrated excellent integrity. Detailed technical results will be presented at the IEEE-IEDM conference in San Francisco this December.
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“With these tests we have demonstrated that our technology allows designing and fabricating fully functional 3D-SIC chips. We are now ready to accept reference test circuits from our industry partners,” said Eric Beyne, Ph.D., program director, Advanced Packaging and Interconnect Research Center (APIC). IMEC’s program on 3D system integration includes partnering for cost-effective research with several other companies. Equipment and materials suppliers include Applied Materials, Disco, EV Group, ICOS, Lam Research, and NEXX. Other players include Amkor, a SATs provider; SMC, a foundry; ICOS, an EDA supplier; Qualcomm, a fabless company; Panasonic, Intel, NEC, Texas Instruments, ST, and Infineon for logic; and Samsung, Micron, and Qimonda for memory.
Key features of IMEC’s 3D-SIC Cu-nail platform approach includes the realization of a Cu-nail after front-end-of-line (FEOL), but before back-end-of-line (BEOL). It takes advantage of the high-aspect ratio Cu damascene technique as opposed to traditional front-end interconnect via processing, and uses a single litho step. Slightly larger features and pitches and a higher aspect ratio are the result. To accomplish the TSV interconnection, Cu-Cu thermo compression bonding is used with simultaneous polymer bonding.
“Achieving coplanar and particle-free surfaces still presents processing challenges,” said Beyne. New cleaning steps will be included in the future.
IMEC is working with the International Technology Roadmap for Semiconductors (ITRS) and Jisso packaging standards group on 3D technology classification. Beyne added that IMEC proposes a classification of the 3D technology based on the interconnection hierarchy, or the level at which the 3D interconnects are made. The industry is debating terminology and who will perform the interconnection steps for 3D integration ??? fab, packaging, or board level assembly. The different 3D interconnect types include 3D-SIP, which uses traditional packaging interconnect technologies with wire-bonded stacked die, stacked packages, or 3D interconnects at the 2nd and 3rd Jisso packaging identified levels. Another flavor is called 3D-WLP for 3D interconnects made post IC passivation or those at the 1st Jisso level. Finally, 3D-IC and 3D-SIC could happen at the IC foundry level, Jisso’s level 0. These would be 3D-SIC with 3D interconnects at the global or intermediate level of the chip-wiring hierarchy. Or they could be 3D-IC, which interconnects at the immediate chip level.
Finding the 3D technology design sweet spot with the best of power, cost, performance, and content remains a challenge. With IMEC’s recent advancements, the technology has matured and the next step is to provide a clear roadmap for bringing these packages to the marketplace. IMEC engineers are using PathFinding, a virtual design flow process to help optimize and evaluate critical points for TSV alignment, electro migration, yield, and test process steps.
-Gail Flower
NEXX Licenses Alchimer Technology for TSV Metallization
BILLERICA MA and MASSY, France – Alchimer S.A. and NEXX Systems, Inc announced that they have entered into an unprecedented agreement aimed at providing the semiconductor industry with a 300mm production platform for wet through-silicon via (TSV) seed deposition in line with Cu fill. Specifically, Alchimer has licensed its eG ViaCoat product for creating thin, conformal copper seed layers for TSV. metallization to NEXX for incorporation into its processes for electro-depositon of high aspect ratio TSVs.
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Via filling represents 26% of the manufacturing cost for manufacturing 300mm TSV wafers, according to a study conducted by Yole Développment (Figure 1). When combined with the costs of isolation, barrier, and seed layer processes, cost totals <30% of the entire TSV manufacturing bill. Steve Lerner, CEO, Alchimer, said eGViacoat was developed to address this technological roadblock, using a proprietary electrografting process that produces conformal, thin, uniform, and adherent copper seed layers, even on resistive barriers. As such, the process offers a reduction in cost-of-ownership (COO) when compared with dry vacuum processes. Lerner added that NEXX’s Stratus toolset is the ideal 300mm platform from which to demonstrate the economic value proposition of eG Viacoat.
“We are pleased to enter into such an agreement with Alchimer at a time when cost reduction is critical to making 3D packaging meet required cost targets,” stated Dick Post, chairman of NEXX Systems, adding that Alchimer’s process is less complex for copper seed than its competitors, which require additional high-cost tool sets.
According to Lerner, under the terms of the agreement, Alchimer will supply its process recipes and the use of chemistries to optimize wet Cu TSV metallization. In addition, the company’s team of scientists and engineers will provide NEXX with support by characterizing and customizing the process to suit a variety of barrier layer materials.
Lerner also emphasized that this is not an exclusive license, rather it allows use of the process. The chemicals will be licensed separately to chemical suppliers.
Pac Tech Malaysia Grand Opening and Advance Packaging Symposium
PENANG, Malaysia – Pac Tech Packaging Technologies reported a successful grand opening celebration of its production facility in Penang, Malaysia in September.
Additionally, its 1st Annual Advanced Packaging Symposium, held concurrently, reportedly drew an audience of 200 from around the world.
The ceremony was attended by local government officials, technical and global business leaders, as well as engineers and managers from within the electronics industry. This facility, which has over 40,000 sq. ft. of production space, will provide wafer level packaging foundry services in high volume including wafer bumping, electroless nickel and gold under bump metallization (UBM), wafer sawing, wafer thinning, die sort, and assembly.
The advanced packaging symposium included a full day of presentations on both business and technology trends within the packaging industry, including: WLCSP, flip chip, and 3D packaging. Pac Tech officials report that based on the success of this event, the symposium will be continued next year and expanded to include more topics related to wafer level packaging.