K&S Celebrates Next Gen Wire Bonders at SEMICON China
04/01/2008
By Gail Flower, editor-in-chief
SHANGHAI — Fort Washington, PA-based Kulicke & Soffa Industries, Inc. launched two next-generation wire bonders just after SEMICON China opened for public viewing. Representatives from the Chinese government and from SEMICON China gave welcoming speeches, as did Christian Rheault, senior VP equipment segment of K&S. Four beautiful women dressed in traditional red costumes held the long ribbon for the three speakers to cut before revealing the new machines to an excited audience. China represented the right setting to introduce these two bonders in a country which would use more of them for interconnecting advanced packages than at any other locale.
 Mark Ding, President, SEMI, China, addresses attendees during the ceremony. |
One wire bonder, the IConnPS High Performance, replaces the current Maxumultra. This high performance bonder addresses the need for accuracy in future challenges demanded by the latest and future packaging technology. It reportedly has +/- 2.0 μm accuracy for sub-35-μm ultra-fine-pitch requirements, advanced looping processes, automatic self-teaching Bond Integrity Test System (Auto BITS), and programmable focus optics for complex stacked-die packages.
The other system is the ConnXPS High Speed Wire Bonder, which replaces the Maxumelite. This bonder emphasizes speed and throughput for use in interconnecting lower pin count ICs and LEDs. The ConnXPS has +/- 3.0 μm accuracy, look-ahead vision algorithms to align and bond simultaneously, and programmable red/blue illumination.
Both wire bonders have a “PS” superscripted title to signify that they are part of K&S’s Power Series product line with fast speed and high accuracy over a large bondable area. To fit a major market location, a Chinese character symbol for “Li” will be used with the product name to indicate power and strength also.
 Ding; Ding Hai Tao, vice chairman, science and technology in Pudong; and Christian Rheault, senior V.P., K&S perform the product launch ribbon cutting ceremony. |
“The market is cautious now,” says Rheault. “However, there is no better time to introduce wire bonders that can increase performance and lower the cost while improving accuracy into the market than the present.” Both the IConn PS and ConnX PS have larger 80 mm bondable area and advanced control systems. Both have programmable power supply systems. They meet future needs by including features for bonding the latest stacked die, Low-k, and multi-tiered packages. The advanced loop and low-loop are premium processes for defining loop shapes. These new bonders are still being qualified by customers, however shipments are expected to begin with the June 2008 quarter.
Judging by the crowd’s focused interest while viewing the overhead video and then photographing the new equipment, the ConnX PS and IConnPS, the market is ripe for innovative change for future growth.
Packaging Sector Holds the Key to Semiconductor Issues
By Françoise von Trapp,managing editor
SCOTTSDALE, AZ — Even with industry-wide slowed economic growth, these are exciting times for the assembly, test, and packaging sector. At IMAPS Global Business Council held Monday, March 17, 2008, in Scottsdale, AZ, speakers Bill Bottoms, Ph.D., chairman and CEO of NanoNexus; and Jim Walker, V.P. of research, Gartner Dataquest, and Advanced Packaging magazine advisory board member; identified the packaging sector as the key to solving semiconductor issues in this consumer-driven marketplace. 3D, wafer-level packaging (WLP), and system-in-package (SiP) have changed the semiconductor electronics manufacturing environment. According to Bottoms, the pace of change is accelerating, particularly in the packaging space.
“We are in a period of unprecedented change. Conventional processes can no longer meet roadmap requirements,” noted Bottoms, in his keynote address. He offered a thorough examination of the technology challenges we face according to the ITRS roadmap, along with suggested solutions. It all comes down to several things: the incorporation of nanomaterials into packaging technologies that address thermal, electrical, and structural issues; novel device architectures; 3D integration to continue functional density; and SiP as the solution-of-choice for the majority of consumer products. Bottoms emphasized the importance of 3D integration throughout his talk, and even joked, “every time there’s a conference on 3D, you can’t get a hotel room. Everyone is working on 3D integration.”
Bottoms’ company, NanoNexus, provides advanced connector and interconnect products based on a unique MEMS technology known as directed self assembly. Bottoms noted that physics is becoming a limiting factor. Industry requirements are changing, with no known solution beyond 2013, he noted. For example, CMOS switches will no longer suffice for increasing density, and a new switch technology will be required. He also talked about conventional lithography, and said a solution is in development for lithography through self-directed assembly. The take-away from his address: Moore’s Law scaling alone can not maintain the pace of progress.
In this climate of accelerated change, with focus on packaging, Walker addressed the packaging supply chain. “The semiconductor business model has to change, because of the consumer-driven market,” he said. “There’s too much to be done, too fast, at too low a cost to do it with the previous business model and be successful.”
 Françoise von Trapp, managing editor, speaks with Professor Bi Keyun, VP of the China Semiconductor Industrial Association, and Steve Adamson, IMAPS president. |
According to Walker, packaging sits right in the middle of the semiconductor supply chain, between wafer fab and final assembly. Traditionally, front-end fabs operate with a gross profit margin of 45%. Packaging firms realize a 20-30% margin, while EMS providers’ have a 5-10% margin. What is happening, he says, is that with wafer-level packaging (WLP), the packaging group is moving up the food chain into the fab’s margin to get the value-add, and at the same time, with system-in-package (SiP) solutions, is taking the value-add from the PCB/manufacturing system. As a result, packaging is growing in both directions, capturing more value-add and realizing better margins. This may explain why the assembly, test, and packaging sector of the industry has been growing at twice the pace as the industry as a whole since 2001. Packaging technologies are in the position to solve issues, he noted.
Steve Corbett, president and CEO, of Cookson Electronics, addressed how materials and process suppliers enable next-generation semiconductor packaging while addressing ever increasing cost pressures. He said that at Cookson, the first choice is to always enable new technology. Then when the technology becomes mainstream, cost has to come down. “There are much bigger contributors to cost than the cost of the materials,” he noted.
For example, using existing technologies to create higher stacks is doable, but is messy, costly, and not high yielding. He cited through silicon via (TSV) processes as a viable solution, although it has challenges – namely finding the perfect fill for high-aspect ratio vias. “If you’re stuck in the world of 2D packaging, you can bring costs down only so far,” said Corbett. “If you can work in 3D you can reduce cost by 49%. If you can enable and deliver at low cost for consumer market, then you can enter the high-volume market.”
Shifting the focus to 3D stacked package technologies, Lee Smith, senior director of business development, Amkor, addressed package optimization for cost-driven applications. Smith was instrumental in Amkor’s development of package-on-package (POP) technologies, which was co-developed with Nokia and Samsung. Using POP’s concept-to-market timeline as an example of leveraging existing infrastructure, combined with a customer-driven application need, Smith explained Amkor’s approach to technology development.
One area not to be ignored is advanced micro-leadframe (MLF) technologies, which are extending application performance envelopes, for example, MEMS MLF, Stacked-die MLF, FC MLF, and LF SiP. There is still a lot of innovation happening in low-cost lead frame technologies. “It’s key to realize 70% of market is made up of leadframe-based packaging technologies,” noted Lee. “They’re still high-volume workhorses in consumer applications.” he noted, and cited Amkor’s recently introduced package platform, FusionQuad, a leadframe-based, plastic encapsulated package that integrates bottom lands within a standard QFP package outline. The combination of both peripheral leads and bottom lands allows for an approximate doubling of I/O within a given body size, or a nearly 50% reduction in body size for an existing lead count.
Scottie Ginn, VP design enablement and packaging, IBM semiconductor research and development center talked about how the company has recognized that the silicon roadmap is robust, and its time to invest more in R& D for packaging. Ginn said they are addressing 3D integration technologies such as TSVs, and merging silicon and packaging groups as more solutions move to WLP. Financial pressures of rising development costs call for a partnership model. “Silicon partnerships can be a model for packaging,” she said. “Collaboration sparks innovation.”
Speaking on behalf of the military electronics segment of the industry was Mark Dimke, Ph.D., senior mechanical engineer at Rockwell Collins. Dimke talked about high reliability microelectronics packaging, noting that unlike the commercial world, which focuses on disposable electronics, the military and avionics industry expects them to last 20-30 years. “We feel fortunate to piggy back on commercial breakthroughs,” he said. “The same problems that affect the cell phone folks are affecting us.”
The final speaker of the day was Professor Bi Keyun, VP of the China Semiconductor Industrial Association. The GBC was the first industry organization to hear what Keyun had to report on the semiconductor industry in China. He began by providing a brief history of the industry in China.
“As you know, the People’s Republic of China developed from a lagging behind agricultural country to a fairly advanced industrial country,” said Keyun. “Now the government set up a scientific development policy of national economy and is promoting self innovation to build an innovative country.” Two of these projects target the semiconductor industry.
He said that the semiconductor industry is developing rapidly, with an average yearly increase of 33.6%, as compared to the the rest of the world’s IC industry which realized only 7.3% growth in 2007. IC design, manufacturing, packaging, and test are not only increasing rapidly, but synchronously as well.
When asked about whether this growth was driven by the 2008 Summer Olympics, held in China, he replied that this was just one factor, and not much of an influence to the packaging sector. “Packaging is expected to experience continued growth at a moderate pace after the Olympics,” he said. He also acknowledged that the initial steep growth rate increase is because they started out so low, with high potential. When it grows to a certain point, it will slow down. It has slowed a bit, but he said growth has been forecasted to continue at least until 2010.
Alchimer CEO Predicts the Demise of Vapor Deposition Processes for TSVs
MASSY, FRANCE — Steve Lerner, CEO of Alchimer SA, Massy, France predicts the demise of vapor deposition processes for depositing nanoscale films in through silicon vias (TSVs) within a year. Alchimer has reportedly developed a proprietary technology called electrografting, intended to overcome the limitations of vapor deposition processes. According to Lerner, after four years in development, the company is negotiating with several foundries and IDMs to adopt their technology.
Electrografting involves chemical formulations and processes for the electrochemical deposition of nanometric films in TSVs. The deposited layers form covalent bonds with the substrate, effectively grafting the two materials together. This wet process is expected reduce costs of processing wafers for high aspect ratio TSVs.
“Dry processes, including PVD and CVD, cannot cope economically with the demands of high aspect ratio TSVs for 3D IC packaging,” says Lerner. “The limitations of these processes are major roadblocks to the advancement of the semiconductor industry – and they’re prohibitively expensive.” A technologist with 29 years’ experience in semiconductor development and manufacturing, Lerner, who was appointed to the position of CEO in March, founded advanced packaging and device companies Alpha Szenszor, GigSys and CS2, and has held executive positions at Amkor, Swire and AME.
Alchimer technology is reportedly easily transferable to industry-standard process lines, so there is no need for investment in new capital equipment.
Names in the News
Two executive-level promotions were announced at Kyocera America earlier this month. Gary Lee was promoted from national sales manager to VP, organic product sales, and will be responsible for expanding Kyocera’s North American business in semiconductor package products based on organic and plastic material technologies. He joined Kyocera in January 2000 and has more than 25 years of experience in microelectronics.
Additionally, Kenji Aonuma, will transfer from the position of GM, international sales division, Semiconductor Components Group, at Kyocera of Kyoto, Japan, to Kyocera America and assume new responsibilities as VP, Asia ceramic products sales. In his new role, Aonuma will be responsible for North American sales of ceramic-based semiconductor package products made by Kyocera business units in Asia. Aonuma joined Kyocera in 1979 and has held sales management positions both in Japan and the United States, including 10 years of prior service with Kyocera America.
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Sergio Perez was named senior V.P. of business development for SV Probe, wholly owned subsidiary of Ellipsiz Ltd. In this role, Perez will be involved in all aspects of SV’s business development, with a focus on memory probe card products and solutions.
Perez brings over 20 years of experience in the semiconductor test equipment industry to SV Probe. He held management positions at Teradyne, Advantest and FormFactor, Inc, and helped found the Semiconductor Test Consortium (STC), an industry group supported by global semiconductor and test equipment companies including Intel Corp., Tokyo Electron Ltd. and Advantest Corp. Perez holds a B.S. in engineering from Harvey Mudd College in Claremont, California and an M.B.A. from Harvard University.
DYMAX Corporation, manufacturer of advanced light curing adhesives, coatings, and curing equipment, announced the appointment of Rob Kleinschmidt as a sales engineer. Kleinschmidt will reportedly play a key role in developing accounts and generating sales in the New England area and surrounding states.
Kleinschmidt has previous experience at DYMAX in applications engineering and in the medical group. He holds a BGS from the University of Connecticut with a minor in business.
Semi-Therm 24 Focuses on Cooling
By Julia Goldstein, contributing editor
SAN JOSE, CA — The technical sessions at Semi-Therm 24 focusing on die and package level cooling showed how advances in modeling, design, and materials improve thermal performance.
One goal of mathematical modeling is to save time and money during the design phase. Researchers at UC Santa Cruz presented a method of speeding up the process for modeling temperature distribution in a die. Speaker Xi Wang described the “power blurring” method as an alternative to finite element analysis (FEA), reducing calculation time from 14 seconds to 0.05 seconds in one example with a 100 by 100 ??m grid size. Wang explained that as feature size decreases and heating unit density increases, FEA becomes cumbersome. this method is designed to model hot spots at a finer level of detail than would be feasible with FEA. The method is still in its early stages, with packages being modeled as solid blocks with a fixed thermal conductivity. Details, such as packages traces that affect the heat dissipation path, could be included in a future version.
Perhaps more important than having modeling software capable of rapid calculation is using mathematical modeling to shorten product development time. Sara Paisner of Lord Corporation discussed the use of a mathematical model to optimize the viscosity of a thermal interface material (TIM). The example she used was thermal grease with two different sizes of filler particles. Modeling can quickly predict the ideal ratio between the two particles sizes to minimize viscosity, replacing extensive DOE efforts. The result is used as a starting point for experiments to fine-tune TIM for a specific application, reducing overall development time from months to weeks. The final result is a TIM with equal or better thermal conductivity, viscosity, and bond-line thickness compared to a TIM developed with a traditional DOE approach.
Bernie Siegal of Thermal Engineering Associates discussed the design of thermal test chips. As Siegel explained, properly designed test chips are important for simulating devices for hot spot investigation or multi-chip package design. One example of a thermal test chip is a device made up of multiple 2.5-mm square cells, each containing two parallel resistors as a heat source that covers most of the cell area. Cells can be assembled into various array sizes, either square or rectangular, to simulate dies of various dimensions. For a large die, a larger cell size may be preferable.
Test chips can be useful for determining the thermal characteristics of new package designs, such as the Integrated Module Board (IMB) analysis presented by Tanja Karila of Imbera Electronics. The design included passive and active devices embedded in a laminate substrate. Thermal resistance ranged from 29 to 65??C/W, depending on the arrangement of thermal vias and the location of the active IC within the build-up structure. Karila explained that thermal performance improved up to a point as the number of thermal vias increased but then reached diminishing return. The optimal number of vias depends on IC size and power density.
Obviously thermal solutions at the package level can impact overall product design. Even though adding thermal vias or using a more expensive material adds cost, such a solution can eliminate the need for liquid cooling in a product, making it a good trade-off. One example is diamond heat spreaders. Dwain Aidala, president and COO of sp3, Inc., a company that manufactures these products, explained that spreaders made from 100% polycrystalline diamond are typically 0.4-mm thick, with a surface roughness tailored to the application. A rougher surface is suitable for use with thermal greases, or a finely polished surface can be metallized with layers of Ti, Pt and Au for connection with AuSn or indium TIMs.