Issue



Solder-free Connectors Using Buckled Pillars


01/01/2009







BY PETER SALMON, Salmon Technologies Inc.

A novel use of stud bumping equipment has enabled the development of buckled pillar connectors for 3D assemblies that are put together with screws rather than solder. While still in development stages, the process is targeting high-powered systems such as servers and routers for aerospace applications.

Aparticularly versatile form of wafer bumping is stud bumping, using either gold or copper wire.1 The equipment required is an adaptation of a traditional wire bonder. A ball bond is made at a first contact pad using heat and ultrasonic energy. The wire is extended in a precise direction and a flying lead is created by terminating the wire, for example using electronic flame-off (EFO). This type of stud bump can be used as a buckled pillar connector, enabling electronic assemblies that are put together with screws rather than solder. With appropriate assembly and testing techniques, this can lead to waste-free integrated assemblies; no good parts are thrown away due to compound yield problems, otherwise known as known good die (KGD) problems.

Why replace ball grid array (BGA) packaged devices?

BGA has become the dominant packaging type for electronic systems, representing 60% of the total packaging revenue in 2008.2 More and more BGA packages use a method of direct chip attach (DCA) called flip chip.3 IBM created the first BGA packages in 1965, using the C4 process. In 2006, IBM introduced Controlled Collapse Chip Connection New Process (C4NP), which was developed to improve yield and reliability while reducing cost.4 However, BGA and C4NP still have two serious drawbacks. First, an epoxy underfill is normally required for die sizes larger than ~4mm. The underfill binds the chip and the substrate together to make a robust package that can withstand the differential stresses induced by temperature cycling, as well as increased levels of shock and vibration. This is a big factor in helping your cell phone survive being dropped. However, the epoxy cannot be easily removed if a chip fails in an integrated assembly. The failure could be a subtle flaw that was not detected by the component test program, or it could be assembly-induced. Since the underfill step cannot be undone, rework is limited or impossible. For an integrated electronic assembly, rework is the process of finding a defective chip and replacing it. Not having a viable path for rework presents a serious economic disadvantage. It means, for example, that underfilled stacked die assemblies will incur an additional cost due to compound yield issues. It also means that integrated assemblies using underfill are limited to ~5 or 6 dice, because reject costs become too great for more complex assemblies. Finally the underfill itself adds both material and process cost.

The second big disadvantage with BGA and C4NP is that they both require solder. The solder may be lead-free, but it still contributes to environmental and reliability problems.5 Solder is reputed to cause more failures in electronic assemblies than any other single cause; the failures range from solder bridging (shorts), to open traces, to corrosion, creep, cracking at brittle inter-metallic interfaces, and tin whiskers.

The Buckled Pillar Solution

Figure 1 is a conceptual drawing showing the versatility of buckled pillar connectors in a new type of integrated assembly. The buckled pillars are formed by a manufacturing sequence that is described in detail in reference 6, including an animation of the process steps.


Figure 1. Customized buckled pillar connectors support many assembly configurations.
Click here to enlarge image

In Figure 1, buckled pillars having potentially five different lengths are required. Because the bonding tool follows a programmed sequence, the different lengths are easily accommodated in an automated fashion. Components are aligned and placed, and the entire assembly is compressed using assembly screws provided in each corner. The screws work against spacers to provide exactly the right amount of compression, enough to buckle the pillars by a few percent in length. This means that the bonding wire material is not stressed above its elastic limit. Accordingly, it acts like a spring. This helps to provide good electrical contact at the receiving cup end, and also provides some design margin to accommodate minor differences in co-planarity of the buckled pillars tips.

The system assembly can accommodate stacked components that use through silicon vias (TSVs), but TSVs are not required in all of the chips. The TSV stacked component in the figure represents a complex component having high electrical performance, but at a considerable cost. The additional cost is associated with the intricate processing to form the TSVs. This typically will represent a good economic alternative only for the highest production volumes. The module or system-level assembly method depicted in the figure accommodates many heterogeneous chip types. Nearly all chips that are currently in use via other assembly techniques (such as conventionally packaged devices on PCBs), can be used in the compact assembly of Figure 1. Conventional packages are eliminated, providing a substantial cost benefit as well as contributing to a more standard electrical, thermal, and mechanical environment. Today, packages encompass so many different types and incorporate so many different design rules with respect to signal integrity and thermal issues, they have become a burden with respect to the design goal of a standardized environment.

It may also be desirable to create semiconductor chip versions of discrete components, such as resistors and bypass capacitors, integrating many of these on each chip. The pad pitch can be as fine as 50µm, using 20µm wire.7,8 Since the ball bond is formed robustly using heat and ultrasonic energy, nearly all pad metals and under-bump metallurgies can be accommodated.

Note that none of the connections include solder. This leads to convenient rework scenarios, wherein a module can be disassembled and a defective chip replaced, using only a placement machine having good alignment capabilities and a screwdriver.

High power IC chips may be provided in a single-high layer at the top of the module as shown. Preferably a soft conductive material, such as indium foil, will be provided at the silicon-copper interface, for the best possible thermal connection. The indium foil fills microscopic voids and helps to eliminate air pockets at the interface. The exposed copper surface at the top of the module is available for heat sinking, providing very low thermal impedance between the transistor junctions in the chip and the heatsink material.

In Figure 1 the substrates are preferably made of copper, and fabricated in a large panel size, such as 12 × 18”. Copper provides good heat distribution and enables the use of a water coolant between module layers. Since the power density in such an assembly is much higher than in a regular PCB assembly, good heat distribution and extraction become mandatory. The interconnection layers shown in yellow are preferably fabricated using direct laser imaging, and this combination of copper cores and laser imaging has recently become available. The build-up layers of the interconnection circuits can be fabricated using fine geometries such as 30µm line and space, again supporting the miniaturized assembly.9

Options for External Connections

In Figure 2a, solder balls have been formed at the bottom face of the module, and the system-in-package (SiP) presents a BGA interface to the outside world. In Figure 2b buckled pillar connections are shown for interfacing between the SiP and a conventional PCB. Figure 2c shows that a flex circuit equipped with buckled pillar connectors may be used for external signals.

A New Cost Tradeoff

Good cost figures are not yet available for miniaturized 3D assemblies as shown in Figure 1. The build-up technology on copper is substantially more expensive than regular PCB technology using epoxy-glass laminates. However, a system-level cost analysis will take into account the following factors: conventional packages for each IC chip are eliminated, the availability of effective rework strategies may lower the cost of yielded assemblies, and the resulting assembly will be more compact and more power efficient leading to savings in space and energy consumption. To illustrate this last point, energy consumption in data centers is currently estimated at 20% of operating costs, and power equipment plus cooling equipment add an additional 24%.10 In addition, once the technology has been shaken down, superior reliability may result from eliminating solder, leading to reduced cost from failures in the field.

Where Will This Technology be Used?

3D assemblies enabled by buckled pillar connectors are a natural fit with high-powered systems such as servers and routers. For blade servers, it is estimated that the new 3D assemblies can reduce space requirements by as much as 50× and weight requirements by as much as 20×. Accordingly, they may become an attractive option for aerospace applications.

Remaining Challenges

Although stud bumping machines exist with the necessary adaptations for making buckled pillar connectors, they are not yet produced by mainstream suppliers and are not yet commercially available. Although lapping and chemical mechanical polishing (CMP) machines and processes exist for planarizing the tips of the pillars, specific processes are still under development. Mechanical modeling is required to confirm the elastic behavior of copper and gold pillars, for specific implementations of wire diameter, pillar length, and compression factor. In the absence of a supporting medium such as wax, the buckled pillars must adequately support embedded chips. Although good shock performance may be achievable with the flexible pillars, this must be confirmed by modeling and experiment. If the technology is combined with water cooling, the primary issue relates to water seals between copper elements. Hydrophobic wax may be used as to keep water away from electronic components, but this must be tested and limits the maximum operating temperature to around 90°C. To take advantage of the proposed more-standardized design environment (excluding chip packages), new design software must be developed and existing software must be integrated into convenient tools. However, the new software may enjoy a much larger market due to wide applicability of the standardized environment.

Conclusion

Although much work remains to validate and test the proposed 3D structures, the potential benefits are substantial. Building on the versatility of stud bumping machines, the overall technique is versatile and can be adapted to many different substrates and chip stack configurations. Compaction factors as high as 50× may be achievable while providing adequate heat removal, effective re-workability, and high reliability. Almost all IC chips that are in use today can be utilized without modification. Although no through silicon vias (TSVs) are required, TSV stacks can be accommodated. Using copper substrates, water cooling may become a practical option.

References

 

  1. Laurie S. Roth and Vince McTaggart, Flip Chip Enabling Technology. http://ap.pennnet.com/Articles/Article_Display.cfm?Section=Articles&Subsection=Display&Article_ID=220943
  2. Electronic Trends Publication, Inc. The Worldwide IC Packaging Market, 2008 Edition.
  3. George A. Riley, Introduction to Flip Chip: What, Why, How. http://www.flipchips.com/tutorial01.html
  4. George A. Riley, C4NP Preliminary Test Data. http://www.flipchips.com/tutorial63.html
  5. John H. Lau and Yi-Hsin Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, 1 edition, 1996.
  6. Peter Salmon, Solder-free Connectors Using Buckled Pillars. http://ap.pennnet.com/display_article/339446/36/ARTCL/none/none/1/Solder-free-Connectors-Using-Buckled-Pillars/
  7. Palomar Technologies. http://palomartechnologies.com/ProductsSolutions/Model8000BallStudBumper.aspx
  8. Kulicke & Soffa. http://www.kns.com/KNS07/Templates/showpage.asp?DBID=1&LNGID=1&TMID=87&FID=514&PID=1405
  9. Sierra Circuits. http://www.protoexpress.com/content/capability.jsp
  10. http://www.apcmedia.com/salestools/CMRP-5T9PQG_R3_EN.pdf

 

PETER C. SALMON, VP can be contacted at Salmon Technologies, LLC, 200 E. Dana St. #8 Mountain View, CA 94041; 650/814-1076; email: [email protected]