Stepping Boldly into The Next Frontier
07/01/2001
The 300 mm pioneers are sowing the seeds for the next critical set of contamination control criteria
by Hank Hogan
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The first wave of 300 millimeter (300 mm) semiconductor wafer fabrication factories has arrived, complete with front opening unified pods (FOUPs) and the beginnings of fully automated material handling systems (AMHS). With it, new contamination control parameters are being established every day, presenting new design options and fresh procedural challenges to the world's top wafer manufacturers. After years of speculation, research and product development, the safest, most direct route to successful 300 mm contamination control is just now being blazed.
For instance, one new option is to build highly automated "dirty fabs." With FOUPs protecting against contaminants and robots shuffling wafers around, tight cleanroom specifications aren't needed — neither are people.
However, the mythical "lights out," "blue jeans" fab also presents its own contamination control challenges. One involves the handling of special wafers, such as those split off from a 25-wafer mother-lot for test or evaluation.
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This "exception" handling leads to a host of questions and presents more opportunities for contamination. "How do you transport it to the sorter? How do you transport it back from the sorter?" asks Doug Keenan, manager of Motorola Inc.'s Schaumburg, IL-based Digital DNA labs. Keenan was heavily involved with Motorola's 300 mm efforts in SC300, the joint venture in Dresden, Germany, between Motorola and Infineon Technologies AG (Munich), before Motorola's active participation ended around October 2000. Today SC300 is operated solely by Infineon.
"With the integration of the automation systems, all these non-standard issues become quite hectic," adds Keenan.
A closer look at 300 mm facilities around the world shows what the contamination concerns are and how they're being handled by these 300 mm pioneers.
Pioneering reports
The oldest 300 mm pilot line is SC300 in Dresden. The line is converting to full production, scheduled for the end of 2002, in an ISO Class 6 (Class 1000) cleanroom. At that time, Infineon will manufacture 256-megabit memory modules using a 0.14-micron feature size process.
Peter Kòcher, vice president and managing director for SC300, reports that as far as contamination control is concerned, there have been "...no specific 300 mm problems identified."
In Tainan, Taiwan, one of the world's leading foundries, Taiwan Semiconductor Manufacturing Co. (TSMC), has also built a 300 mm pilot line. In production since December 2000, TSMC's pilot is several times larger than SC300 in terms of maximum wafer output and also features more automation, an overhead transportation system and a ISO Class 5 (Class 100) cleanroom. The company ensures the cleanliness of its products through FOUPs and tool-specific minienvironments that are ISO Class 2 (Class 0.1). This approach seems to be working.
"TSMC has run 0.18-micron, 0.15-micron and 0.13-micron processes on the pilot line and obtained good yields for each," says N.S. Tsai, director of TSMC's 300 mm project.
Intel Corp. (Santa Clara, CA) also has a development fab, RP1, the first 300 mm-specific research facility in the world (see page 1). Located in Hillsboro, OR, the facility began operations the first half of this year.
There is a full 300 mm production line, built by Trecenti Technologies Inc. in Hitachinaka, Japan. A joint venture between Hitachi Ltd. and Hsinchu, Taiwan-based United Microelectronics Corp. (UMC), this fab is a six-floor monster capable of pumping out 40,000 300 mm wafers per month. It is an ISO Class 6 (Class 1000) cleanroom, built from the ground up to manufacture 300 mm wafers. Today this is done using a 0.18-micron generation process. The fab has produced silicon for customers and is in the midst of ramping up to full production, a procedure that will take years, the company says.
UMC is building another factory, this time in Taiwan, which will be equal in size, capacity and capability to the Trecenti facility. It's scheduled to begin pilot production the second half of this year. Like Trecenti and TSMC's pilot line, the new fab will be used as a silicon foundry. According to Jim Ballingall, vice president of worldwide marketing for UMC, the Taiwan fab will run in an ISO Class 5 (Class 100) cleanroom.
Building lights out?
For UMC and its production facilities, the contamination control motto could be summed up as "more is less"—more automation means fewer people.
"We're building truly lights out fabs, which don't require operators," says Ballingall. "The FOUP is transported interbay by an overhead transfer system, and then it's handed off to a rail-guided vehicle in the bay to move it from equipment to equipment intrabay."
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On the other hand, UMC's motto could also be "less is more"—fewer people leads to less contamination and fewer defects. That, in turn, results in either higher or more consistent yield. That's not an effect confined to UMC and its factories. TSMC, for instance, reports significantly reduced yield variations, which company spokesman Dan Holden attributes to FOUPs and the AMHS.
Michael Brian, vice president of systems and software solutions at Asyst Technologies Inc. (Fremont, CA), has seen this before. Before FOUPs and 300 mm wafers, Asyst had a philosophically similar mid-1980s product line, the Asyst-SMIF (Standard Mechanical Interface) System. Like FOUPs, SMIF provides an enclosure that travels with wafers and keeps them contaminant free.
One of the effects seen by Asyst with SMIF and factory automation has been improved and more consistent yield. Some of this is from particle and contaminant reduction, but some is from the automation itself.
Consider what happens when a wafer measurement must be taken in a fab. The typical, non-automated approach might be to grab a wafer with a pair of tweezers, carry it to a nearby metrology tool, stick the single wafer on the instrument's stage, measure the wafer, walk back with it and then drop it into the lot. That's quite a bit of manual handling.
"When we would go in and convert a fab to SMIF and get rid of those kinds of operations, we would see yield improvement, besides the particle control...from things like people not dropping wafers out of tweezers and not scratching them while putting them in and out of cassettes," says Asyst's Brian.
That yield improvement adds to the particle reduction from using the traveling, clean containers. The magnitude of the yield increase varies with the cleanliness level of the fab, as well as device linewidth geometries and dye size. Brian notes the increase could be anything from a few percent to 20 percent, in extreme cases.
Play nice
There are, however, at least two major contamination challenges to turning out factory lights. The first is that some wafers will have to be split off for measurements, special work requests or for engineering and maintenance purposes. The second hurdle is getting everything to work together on both a hardware and software level.
As for the first challenge, there are many instances were a single wafer may be plucked from a lot. For instance, in-line metrology frequently demands a single wafer measurement. One suggested solution is to build the measuring instrument as part of the fabrication tool. That avoids the problem of opening a FOUP, extracting a wafer, making a measurement and then integrating the wafer back into the mother lot. It also eliminates extra trips that place an added load on the AMHS.
The difficulty is that many measurement instruments have throughputs equal to dozens of fabrication machines. Thus, the ideal is to have one measuring instrument for many fabrication tools. Because it's not cost effective to have metrology instruments sitting idle, wafers will still be separated out. Such measurements are a known part of the process flow, so this procedure could be automated.
What can't be predicted, however, can't be automated. In theory, an AMHS can handle all wafer movement.
"In practice, the real world is not perfect, and you're going to have a need for special work requirements in which you need to have the wafers sorted," says Rick McFarland, director of strategic objectives and standardization for Motorola's semiconductor group and a leader of the company's 300 mm efforts.
Such special handling will need to be done in a clean environment, will require careful attention to material tracking, and will demand flexibility in the automation system. Special handling also opens up all sorts of contamination possibilities, and that requires contamination control.
But this task is complicated by the second hurdle: getting everything in a fab to play nicely together. This problem breaks down into hardware issues and software concerns. The hardware interoperability can be solved by specifying that all FOUPs and the AMHS come from a single company or by requiring strict adherence to international standards.
That option isn't available with software. A factory may have hundreds of tools, made up of dozens of different types of gear and supplied by a swarm of manufacturers. Interfacing all of this is no easy task.
"I would call it a major challenge," asserts Brian of Asyst.
Single wafers and tall stacks
There are, to be sure, additional 300 mm contamination control concerns. Some involve the manufacturing tools. In theory, these new tools should contribute only half the contaminants of the previous, 200 mm generation equipment. That's because in the tool specifications, the requirement was that the particles added per wafer had to remain the same at 300 mm as it had been at 200 mm. Yet, a 300 mm wafer has 2.25 times the surface area of a 200 mm wafer. Thus, the tool-added contaminant level per square centimeter of 300 mm is supposed to be less than half that of 200 mm wafers.
The actual results of this approach show that some work still needs to be done.
"Our biggest concern now is defects that appear to be generated from certain tools. We are working closely with equipment vendors to resolve this problem," explains TSMC's Tsai.
The same equivalence trick was used for tool throughput, with key tools, such as photolithographic machines, being required to produce as many wafers at 300 mm as they did at 200 mm.
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Vendors have responded to these demands in a variety of ways. One approach is to go to single-wafer processing. Running wafers through tools in smaller batches boosts throughput by eliminating dummy wafers and by reducing waiting time. It may also pay benefits in terms of contamination control.
"The management of the process chamber is simplified with the single wafer design. There's far less surface area adjacent to the wafer. In terms of accumulation of material and its redistribution to the wafer surface during processing, single wafer systems have a significant advantage," says Tom Callahan, strategic marketing manager of high current implanters at Varian Semiconductor Equipment Associates Inc. (Gloucester, MA).
In particular, Callahan points to improved performance in single wafer versus batch systems in the areas of implant species cross contamination. There are also improvements in the areas of metallic and particle contamination. The engineering of the single wafer system ensures these enhancements.
Yet, there are some "physical realities" that engineering simply can't solve. Two bodies can't be in the same space at the same time. Larger wafers require more storage, and cleanroom space is at a premium. So semiconductor manufacturers are looking at remote storage, where FOUPs and wafers are temporarily staged in areas either above or below a cleanroom. That leads to the need to extend the AMHS and devise methods to cleanly move silicon into and out of such areas.
Bye-bye blue jeans
Depending on how the automation and other problems are solved, fabs may or may not be built lights out, but nobody will be wearing blue jeans while working in them. The sloppiest specification of 300 mm facilities built so far is ISO Class 6 (Class 1000) and the tightest is ISO Class 5 (Class 100).
UMC's Ballingall notes that going into Trecenti, the first mass production 300 mm wafer fab, requires the same type of gowning procedures used in other semiconductor facilities. This is despite UMC's own experience with SMIF, which showed the traveling clean containers to be relatively immune to outside cleanroom conditions.
Motorola's McFarland reports the use of the FOUP minienvironment in SC300 allowed the cleanliness of the fab to be relaxed without impacting yield—that relaxation cuts ongoing operating expenses such as energy costs.
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So why isn't anyone manufacturing semiconductors while wearing blue jeans?
"The real issue is the comfort level in the fab, the heat load reduction. It's really not driven any longer by the particles," remarks Dave Gross, manager of manufacturing systems for the wafer fab group of Advanced Micro Devices Inc. (Sunnyvale, CA). "To move the amount of air in the fab just to manage the heat load from the larger tools and the people in the fab, it drives you down in the area of cleanliness that we have today anyway."
With that said, Gross notes that the lack of blue jeans doesn't imply a lack of comfort. AMD's latest factory, located in Dresden, Germany, is a SMIF-equipped fab. There the company has gone to special clothing worn under the cleanroom garments. This wasn't done out of concern for particles. Instead it was driven primarily by the comfort of the cleanroom workers.
The company feels this experience with SMIF will supply valuable information for an eventual 300 mm facility.
The 300 mm majority
When AMD builds a 300 mm fab, it'll be joining the majority of the semiconductor industry. Strategic Marketing Associates (SMA; Santa Cruz, CA) tracks wafer fab construction activity. Starting with a spike of over 60 percent in August 2000, the figures collected by SMA show a strong trend toward 300 mm production (see figure on p. 20). The latest data is from March 2001.
"I think the important thing about the graph of 300 mm as a percent of all fab starts is that, since August, 300 mm has accounted for more than 50 percent six months out of eight," says SMA president George Burns. Preliminary data from April also shows more than half of all new wafer fabs started to be the 300 mm variety.
These figures are backed up by some of the leading semiconductor manufacturers. For example, starting in 2001, all new TSMC fabs will be 300 mm facilities, according to TSMC's Tsai. In the 2004/2005 timeframe, 50 percent of all TSMC capacity will come from 300 mm fabs.
This is happening despite a 15 percent downturn in semiconductor revenue projected by Gartner's San Jose-based Dataquest unit. Cahners In-Stat Group (Scottsdale, AZ) has a similar gloomy forecast.
That, however, hasn't slowed down the rush toward 300 mm. According to UMC's Ballingall, the company has not cut back on its 300 mm expansion. Instead, with the downturn, UMC cut off planned 200 mm fabs. The 300 mm effort remains on what the company characterizes as a brisk schedule.
Not everyone is moving as quickly. Motorola, for example, doesn't project a 300 mm facility until 2003 or 2004. AMD has not publicly stated when or where its next facility will be built. Nor has the company revealed what wafer size the fab will be. According to Gross, AMD, as might be expected from a California-based company subject to rolling blackouts, is quite concerned about the power consumption of a 300 mm fab.
Finally, some companies have absolutely no plans to build a 300 mm facility. German startup Communicant Semiconductor Technologies claims to be the world's first foundry focusing on the specialized needs of the communications industry. Using a silicon-germanium carbon BiCMOS process and backed by technology partners Intel and the German Institute for Semiconductor Physics, Communicant plans to pump out 30,000 200 mm wafers per month in a SMIF-equipped fab beginning in the first quarter of 2003.
Klaus Weimer, Communicant's CEO, points to the fact that telecommunications chips tend to be small as a reason to stay at 200 mm. He also notes that the process being ported from Intel and the Institute was developed on 200 mm wafers. These reasons, taken together, explain why the company plans to stay with the smaller wafer size. They are reasons others might cite as well.
As Weimer explains, "There is really no business reason because we don't gain a cost advantage, or the cost advantage compared to the risk is essentially negligible."
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300 mm Fab Update -- see table
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Other announced plans (listed alphabetically):
AMD plans to build 300 mm Fab 25 by 2004.
Intel's 200 mm Fab 22, under construction in Chandler, AZ, will transition to 300 mm in the future.
Micron Technology's pilot line at Lehi, UT, USA, is on hold as of 1Q2001.
Mitsubishi Electric plans to build a 300 mm fab in Kochi Prefecture, Shikoku, Japan, for operation by 2003.
Mosel Vitelic, while continuing with its ProMOS JV, is holding plans to build 300 mm fabs in Taiwan and Canada.
Nanya Technology has plans to build two 300 mm fabs by 2005.
NEC plans to build a 300 mm fab (G-line) in Roseville, CA, USA, for operation by 2003.
Nippon Foundry plans to build a 300 mm fab in Tateyama, Japan, for ground breaking in 2002.
Powerchip Semiconductor's board renewed approval, on March 1, 2001, for construction of 300 mm Fab 2.
Trecenti Technology plans to build 300 mm Fab 2 in Ibaraki, Japan; tentative start date 2002.
TSMC has begun (4Q2000) construction of a shell in Tainan that will eventually become 300 mm Fab 15.
UMCi plans to add 300 mm Module B to its Singapore fab, which is now under construction, after Module A is running.
Winbond Electronics plans to build a 300 mm fab in Taiwan (location TBD) for ground breaking by 2H2001.