As ICs stack up, cleanliness levels may follow
10/01/2008
By Hank Hogan
There’s a growing consensus that the semiconductor industry has no place to go but up???literally. Driven by performance and cost needs, the industry is developing manufacturing processes that stack integrated circuits atop one another, adding another dimension to previously flat structures. There could be a cleanroom impact of this journey into the third dimension.
Jan Vardaman, president of the consulting company TechSearch International (Austin, TX), notes special care might be needed for 3D integration done at the packaging level. “If we are talking about through-silicon via wafer to wafer and die to wafer, the assembly of these will need to take place in a clean environment. Contamination would mean defects.”
“Most of our stuff is done in a Class 1000-type cleanroom,” says Robert Patti, chief technology officer for 3D chipmaker Tezzaron Semiconductor (Chicago, IL and Singapore).
The company uses a copper thermal-diffusion bonding and through-silicon interconnect processing, thinning the bottom wafer down from some 750 µm to 450 µm or so. The next and subsequent wafers are ultimately thinned down to less than 10 µm.
Some of the company’s processing areas have microenvironments that are roughly Class 100 or ISO Class 5. That is much cleaner than what is traditional for an assembly area, acknowledges Patti.
However, 3D integration could take place elsewhere in the process. An August announcement from fabless semiconductor company BeSang Inc. (Beaverton, OR) reported on the company’s claimed breakthrough in 3D chips. Working with Stanford University’s Nanofabrication Facility and the Daejeon, Korea-based National NanoFab Center, BeSang used its three-dimensional process to make chips with 128 million vertically oriented devices. The upper chip was done in a thin silicon layer and connection to the lower chip was through conventional vias.
According to Joon Chung, director of operations for BeSang, the company’s approach uses mainstream CMOS and silicon-on-insulator (SOI) processes in a standard cleanroom. The result is some added complexity but no need for additional cleanroom floor space or any new cleanroom challenges. “A few new steps are added to the current process. We don’t think there will be a problem,” says Chung.
Ed Myers, technology manager of the Stanford facility, notes that the BeSang process is based on techniques and equipment that aren’t exotic. “The tool set is the same as for silicon,” he says.
No matter what the cleanroom impact or how the chip stack is achieved, though, 3D processing attempts to solve some significant problems confronting semiconductors. The goal is faster operation, greater density, and lower cost, all desirable attributes. It is believed that going vertical will bring these benefits because it allows memory cells to be placed above logic elements, for example. In effect, the chip folds onto itself, thereby decreasing its size and increasing its density.
The combination of multiple layers can be particularly potent for such applications as an image sensor. The top layer can be a photosensor, with simple processing, while the logic, with its more complicated processing, is in the bottom layer. The resulting sensor doesn’t need microlenses and has a higher efficiency than its flat counterpart, according to Tezzaron’s Patti.
He believes such an image sensor will be the first high-volume application using Tezzaron’s technology. This will be because the 3D chip offers a better overall solution, he says. “The cost per pixel is less than in a 2D solution.”