Paradigm changes in 3D-IC manufacturing

07/01/2013

THORSTEN MATTHIAS and PAUL LINDNER, EV Group, St. Florian, Austria

The process flows applied today for real product manufacturing are quite different from the process flows initially proposed for a universal 3D IC.

S uccessful 3D-IC prototypes have been demonstrated for many different devices. However, while for some applications 3D-IC architectures have been smoothly integrated into products despite their technical complexity and the omnipresent cost pressure, for other products there seems to be a long list of issues (cost, yield, thermal issues, lack of standards, lack of design tools, etc.) that prevents adoption of 3D-IC integration in the near future.

Common wisdom is that a technical innovation is first introduced for high-performance, high-margin applications, for which the performance gain can bear the additional cost. As the technology becomes more mature, costs are reduced and an increasing number of applications adopt the new technology. A good example of this in the semiconductor industry is flip chip bumping. However, if we look at 3D ICs the situation is not so clear. While it is true that some "cost does not matter" applications in the science, military or medical field use 3D stacking, many high-end devices (most notably CPUs) do not yet use 3D stacking. However, some of the lowest-cost devices in our industry such as light emitting diodes (LEDs), micro-electromechanical systems (MEMS) and image sensors have successfully implemented 3D-IC technology.

Is the adoption of 3D-IC technology in high-volume, low-cost devices evidence of its technical maturity? In his famous book "The Innovator's Dilemma" Harvard Professor Clayton Christensen introduced the idea that any innovation and its potential for industrial adoption should be assessed in the context of their respective value networks [1]. The value network of a product (e.g. a CPU) is defined by the sales critical parameters (e.g. computing power, clock speed, on-chip cache memory and price) and by the expectations of the current customers about future requirements. Any innovation that improves the sales critical parameters within the current value network is defined as "sustainable innovation". Innovations that do not improve the sales critical parameters within the current value network are defined as "disruptive innovations". In his studies Prof. Christensen concluded that innovations cannot be introduced in value networks where they are considered "disruptive" no matter how technically mature, cheap or well established for other applications they are. However, in a different value network where the innovation is sustainable, the users can hone their skills and build expertise. If the expectations within one value network change, then innovations can be introduced very rapidly.

For example, for FPGAs the 2.5D interposer enables smaller die sizes, which allowed 28nm technology to be introduced at a reasonable wafer yield at an earlier point of time. The result of introducing interposers for FPGAs is that an FPGA with more and faster transistors can be manufactured earlier. Therefore, the 2.5D interposer for FPGAs is a sustainable innovation. For mainstream semiconductor devices like memory, Moore's Law is (or at least was until recently) a good proxy of the value network. If you put a TSV on a chip, you cannot put transistors onto the same area. TSVs reduce the number of transistors on the chip and increase the price per transistor.

Is 3D integration ready for volume production?

At first glance TSV and 3D IC are disruptive innovations. TSVs and die stacking have already been successfully implemented in high-volume manufacturing for CMOS image sensors, despite the fact that the combination of high technical complexity, immature technology, and low-cost/low-margin devices seems like a very unfavorable situation. From the pure technical point of view 3D-IC image sensors seem more challenging than other devices, such as stacked memory. The TSV density is higher, the TSV diameter is smaller, the pitch is smaller, the wafers are thinner and wafer-to-wafer stacking is necessary. However, the transition from front-side illuminated image sensors to backside illuminated image sensors as well as the current transition to 3D-stacked image sensors (where photodiodes and digital signal processing are manufactured on separate wafers) have resulted in technical improvements within the existing value network, including better resolution, smaller pixels, better signal-to-noise ratio, higher image processing speed and higher bandwidth.

When engineers first looked at developing 3D IC technology, they did not design a 3D-IC device from the get go, but rather started with separate technical milestones. In most cases, the first milestone was to manufacture a daisy chain with 10, 1000 or 10000 TSVs. The focus was primarily on the unit processes for TSV manufacturing. The second milestone was to manufacture a thin die with TSVs and bumps on both sides, which might eventually be used in a real system. The paradigm for thin-wafer processing in early 3D/TSV development was that a temporarily bonded wafer had to withstand any kind of backside processes. Thus, flexibility and broad process windows were most important. In theory the idea to completely manufacture individual thin chips is very attractive as it enables known good die (KGD) manufacturing and fits into every possible integration scheme and business scenario. However, in practice this approach results in overly complex integration schemes, which are not optimal from a yield and cost perspective.

FIGURE 1. Exemplary process flow for 2.5D interposer with 3D-stacked chips (EVG patent pending) [2]

This paradigm changed when product groups began to adopt thin-wafer processing for specific products. Now the highest goal was to maximize profit on the product, and yield and cost of ownership were optimized for the entire process flow for chip and package???often abandoning previously considered universal one-size-fits-all solutions and resulting in completely new integration schemes. For example, whereas previous R&D efforts went into very thick films with the idea to embed C4 (flip chip) bumps, today's 3D-IC devices primarily apply bump-last process flows, which use very thin adhesive layers. This has the advantage of reduced cost, better film thickness control and higher yield as a result of avoiding bump damage caused by post-bump processing. Transitioning from very thick to thin films also reduces the duration of the baking steps for curing the films???enabling the design of temporary bonders with more than twice the throughput. FIGURE 1 shows an exemplary process flow for 2.5D interposers with 3D-IC chips stacked by chip-to-wafer bonding [2]. Another key 3D-integration concept is overmolding prior to debonding, which allows double-side processing on ultra-thin wafers while avoiding thin-wafer handling altogether. As shown in FIGURE 2, after chip stacking the entire wafer is overmolded while the thin interposer wafer is still bonded to the carrier wafer. This overmolding compound creates a rigid film on top of the thin interposer wafer.

FIGURE 2. Overmolding prior to debonding is a key integration concept.

An analysis of the published process flows for 3D-IC manufacturing today shows that bump-last process flows and overmolding prior to debonding have already been implemented. Within TSMC's Chip-on-wafer-on-substrate (CoWoS) process flow [3], the chip stacking on the interposer occurs before the backside of the interposer is processed. It is a complete reversal from the previous paradigm that individual chips have to be tested prior to stacking. KGD manufacturing of the interposer is not possible with this process flow. However, from the pragmatic manufacturing point of view it allows manufacturing of thin wafers while avoiding handling of thin wafers. Implementing a bump-last approach also increases flexibility and eliminates the risk of bump damage during stacking. Texas Instruments' stacked wafer chip-scale package (WCSP) platform separates the interposer and chip manufacturing, which is more in line with the classical foundry/OSAT model [4]. However, like the CoWoS process flow, it allows the creation of ultra-thin interposers without the need to handle thin wafers at any point during manufacturing or assembly.

FIGURE 3. Process Flow for backside illuminated image sensors (Courtesy of Yole D??veloppement)

FIGURE 3 shows a typical process flow for backside illuminated image sensors. An ultra-thin device wafer is created by permanent wafer bonding to a silicon carrier wafer. After a series of process steps this wafer stack is bonded to a glass wafer, which then acts as a carrier wafer for further processing. This allows thinning of the initial silicon carrier wafer and creating TSVs. Essentially, the original carrier wafer now becomes an interposer wafer. An important aspect is that in this case the image sensor-interposer connection is bump-less, which allows interconnects with a fine pitch down to less than 2 micron while at the same time saving the cost to create bumps.

One paradigm of 3D-IC manufacturing was that the industrial adoption will first start with chip-to-chip stacking (C2C), later on move to chip-to-wafer-stacking (C2W) and finally move to wafer-to-wafer stacking (W2W). W2W integration has the fundamental limitations that the dies have to have the same size and that a good die might be stacked onto a defective die. However, with respect to manufacturing complexity it has a lot of advantages; first and foremost that it allows parallel processing of all dies on the wafer. In fact, it is remarkable that W2W stacking with TSVs has been successfully implemented for many devices already, especially low-cost devices. Due to the successful implementation of backside illuminated image sensor manufacturing on large substrates, a 300mm wafer bonding infrastructure has been established in the industry. Fusion wafer bonding (as shown in FIGURE 4) is the method of choice for bump-less chip-chip interconnects for both via-last integration for oxide-oxide bond interfaces and via-middle integration with hybrid oxide/metal bond interfaces. Fusion wafer bonding is also a key technology for monolithic 3D integration as it can be used to transfer thin layers of silicon on top of an already processed wafer.

FIGURE 4. The EVG GeminiFB fusion wafer bonding system integrates wafer cleaning, LowTemp?? plasma activation, SmartView?? wafer-to-wafer alignment system and wafer bonding all in one system.

One interesting aspect of W2W integration is that it enables ultra-shallow TSVs. It is possible to implement 1 ??m x10 ??m or 1 ??m x 5 ??m TSVs without the need to deal with 5 ??m or 10 ??m thin wafers. As the cost of TSV manufacturing is strongly correlated to TSV depth and TSV aspect ratio, W2W integration allows significant cost reduction. W2W integration also enables much better die-to-die alignment accuracies compared to C2C and C2W thereby enabling the usage of small TSV diameters and fine TSV pitch (FIGURE 5).

FIGURE 5. The EVG SmartView?? aligner provides sub-micron wafer-to-wafer alignment accuracy enabling fine pitch interconnects. (Courtesy of SiliconFile Technologies, Inc.)

Stacked memory is a potential application for W2W stacking as the dies have the same size. It is questionable whether die testing prior to stacking can be implemented for memory. If testing prior to stacking were not to be implemented then W2W integration is a natural choice due to reduced TSV cost and precise alignment capability. In this way, the image sensor has paved the way for W2W integration for memory.

Conclusion

3D integration can provide many benefits, but only where it can prove to be a sustainable innovation. TSV and 3D chip stacking have been successfully implemented for devices like FPGAs and image sensors, where 3D IC was a means to improve the sales critical parameters of the devices. Its implementation in high-volume manufacturing occurred despite high technical complexity and the omnipresent cost pressure, which is compounded for low-cost devices. Innovation theory suggests that once a new technology has been established for one product, it can be adopted very rapidly by other products.

The process flows applied today for real product manufacturing are quite different from the process flows initially proposed for a universal 3D IC. Chip manufacturing and packaging process flows have since been concurrently optimized. Today, C4 bumps are generally manufactured as late as possible in the overall manufacturing process. Thin-wafer processing is a key competence, but in many cases thin-wafer handling after debonding has been eliminated by either overmolding or wafer bonding to another device wafer prior to debonding. Image sensors apply the most radical concept of W2W stacking, which allows reduced manufacturing costs due to bump-less integration and ultra-shallow TSVs. 3D ICs based on W2W integration is a reality today.

References

1. C. Christensen, "The Innovator's Dilemma," Harvard Business School Press, 1997

2. T. Matthias et al., "From unit processes to smart process flows ??? new integration schemes for 2.5D interposer," Chip Scale Review, March/April 2013

3. P. Garrou, "Insights from the Leading Edge 135: UMC/SCP Memory on Logic; SEMI Europe 3D Summit Part 2," Solid State Technology, February 12, 2013

4. R. Dunne et al., "Development of a stacked WCSP package platform using TSV Technology," Proc. IEEE Electronic Components and Technology Conference (ECTC) 2012

THORSTEN MATTHIAS is business development director at EV Group, St. Florian am Inn, Austria. Tel: +43 676 84531148, e-mail: [email protected]. PAUL LINDNER is executive technology director at EV Group.

Solid State Technology | Volume 56 | Issue 5 | July 2013