The challenges of sub-20nm shallow trench isolation etching

06/03/2013

Hui Zhou, Xiaosong Ji, Sunil Srinivasan, Jim He, Xuefeng Hua, Ankur Agarwal, Shahid Rauf, Valentin N. Todorow, Jinhan Choi, and Anisul Khan, Applied Materials, Inc., Santa Clara, CA

Major challenges for sub-20nm STI etching include intra-cell depth loading, across-wafer uniformity, etch profile control near the wafer edge, and propensity for pattern collapse.

Shallow trench isolation (STI) is used for device isolation in state-of-the-art semiconductor process technologies [1]. For optimal transistor performance and desired yield, the line critical dimension (CD) and the trench depth must be tightly controlled [2]. As feature sizes scale below 20nm, the aspect ratio of the isolation trench can be as high as 20:1. Given the small space CD, variation in trench width (e.g., from double patterning) is no longer negligible, and the subsequent aspect ratio dependent etching effect can lead to non-uniform trench depths [3]. Consequently, minimizing intra-cell depth loading is crucial.

As feature sizes scale, profile uniformity across the wafer and, in particular, near the wafer edge assume greater importance. The outer edge (10mm) of a 300mm wafer accounts for over 10% of total devices that yield. But the edge area is characterized by discontinuities of materials (wafer to focus ring/process kit transition), and electrical and thermal properties (due to the wafer overhang on the electrostatic chuck). Consequently, the plasma sheath characteristics are not necessarily similar to those over the center of the wafer, leading to significant impact on STI features near the wafer edge. Both of these aspects must be managed simultaneously for sub-20nm features.

Aside from the above challenges for sub-20nm features, some new issues also arise. One is the potential for line collapse, which can substantially reduce production yield. Pattern collapse has been a major problem for lithography resist, and numerous research papers addressing this issue have been published [4-7]. Owing to their low Young's modulus of 1-5 GPa, lithography resist patterns succumb to capillary pressure during the drying process [8]. Silicon, unlike a typical resist material, is much more rigid with a Young's modulus of ~150 GPa [9] and is usually immune to pattern collapse for STI etching when line widths are on the order of 100s nm. However, line collapse has been increasingly observed in sub-20nm STI features, especially after wet cleaning.

In this paper, we discuss the above four challenges (intra-cell depth loading, wafer edge profile, across-wafer etch uniformity, and line collapse) in etching sub-20nm STI features, using experimental results from the Applied Materials inductively coupled plasma silicon etcher. Some general guidelines to overcome these challenges are also reviewed.

Intra-cell depth loading

In most cases, high aspect ratio features etch more slowly than low aspect ratio features due to the transport limit of etchant in the trenches [3]. In other words, the etching rate of a wider trench is higher than that with a smaller CD. As the CD scales below 20nm, any space CD variation is no longer negligible compared to the CD and leads to depth loading with plasma etching. Ions are less affected by trench shadowing due to their higher directionality resulting from acceleration within the sheath. Therefore, shadowing of neutral species ??? the radicals, molecules, and the etching products ??? dominates aspect ratio dependent etching. Through our process developments, we identified three general rules that are most effective for minimizing intra-cell depth loading during sub-20nm STI etching:

1. Prevent further space CD variation by maintaining a clear trench with thin sidewall protection film.


2. Alleviate the transport limit of neutral species between wider and less open trenches by using pulsed plasmas.


3. Make the process less radical driven and more ion driven by using high-energy etchant ions, such as Cl⁺ or Br⁺.

Sidewall protection is critical in high aspect ratio etching [10]. The passivation layer protects the trench sidewall from etchant species and helps maintain a straight sidewall profile. The efficiency of the protection layer depends on the film composition and its thickness. However, a thicker film also reduces the space CD, which can have a significant impact in sub-20nm STI etching. A thin sidewall passivation layer is therefore desired for minimal reduction of the space CD. Note that during silicon etching, the trench can get blocked due to deposition of the etching radicals or redeposition of etching byproducts. The trench therefore also needs periodic cleaning. A practical approach is to have alternating trench cleaning, passivation, and silicon etch steps. The exact order may vary, but throughout the process, a clear trench should be maintained with a thinnest possible sidewall protection film.

FIGURE 1. STI etching profiles using 13MHz bias power with (a) continuous wave plasma and (b) pulsed plasma (processes are not fully optimized).

Continuous wave plasma etching technology has served microelectronic fabrication very well in most applications, but with the transport limit of neutral species for STI etching, we must consider an alternative plasma etching regime, namely, a pulsed plasma. Pulsed plasma is transient, which is different from continuous wave operation [11], alleviates the transport limit. During the off cycle, the radicals/ions/byproducts have extra time to move out of the trench or act independently on the sidewall, for better sidewall polymer deposition management. FIGURE 1 shows an example of improved intra-cell depth loading using pulsed plasma. STI features etched using continuous wave plasma etching (Fig. 1a) have large intra-cell depth loading due to space CD variation while those etched using a pulsed plasma (Fig. 1b) have significantly less intra-cell depth loading in spite of the same space CD variation.

FIGURE 2. Modeling results of ion energy distribution versus bias frequency.

Unlike neutral species, ions are less susceptible to shadowing effects due to their acceleration by the sheath electric field, which leads to more directionality. Consequently, intra-cell depth loading can be reduced if the silicon trench formation were dominated by ions (Cl⁺ or Br⁺) instead of radicals. Ion dependent etching can be realized by increasing ion energy or ion density. To increase ion energy, one can elevate the bias power or lower the bias frequency. As shown in FIGURE 2, model-predicted ion energy distributions for varying bias frequencies at constant bias power indicate that ion energies can be increased with lower bias frequency. In fact, pulsed plasma and lower bias frequency can be combined to reduce depth loading. FIGURE 3 shows STI etching profiles with 2 MHz bias power operated in continuous wave or pulsed plasma mode. While the high ion energy approach with lower bias frequency of 2 MHz reduced the intra-cell depth loading (compared to the trench profiles in Fig. 1), the pulsed plasma with 2 MHz bias power showed the least depth loading. Besides decreasing the intra-cell loading, the high ion energy etching approach has another benefit of maintaining a flat trench bottom. This facilitates a uniform etching front, which is desirable for achieving a high production yield.

FIGURE 3. STI etching profiles using 2MHz bias power with (a) continuous wave plasma and (b) pulsed plasma (processes were not fully optimized).

By following the three guidelines, we minimized intra-cell depth loading of STI trenches with similar CD, for such applications as NAND STI. The three rules also have the potential to significantly reduce depth loading between dense areas and wide open regions. For example, a typical DRAM STI pattern, as shown schematically in FIGURE 4, is designed to have trenches with narrow openings between the cells and wide open regions at the cell ends as illustrated in [12, 13]. We have also applied the three general rules for DRAM STI etching and achieved promising results.

FIGURE 4. Plan view of a typical DRAM STI pattern, with narrow open area between cells and wide open region at the cell ends, as illustrated in [12, 13].

Edge profile and uniformity

Two other issues are also challenging for sub 20nm STI etching. These are edge profile control and uniformity tuning across the wafer. These two issues originate from the nature of plasma distribution inside the reaction chamber, which is often beyond the capability of process tuning. The fundamental solution would be implementing novel hardware to achieve more uniformly distributed plasma.

FIGURE 5. Schematic of plasma sheath curvature due to discontinuities at the wafer edge.

Three main kinds of discontinuities occur at the wafer edge: 1) material discontinuity from the silicon wafer to the support ring; 2) geometrical discontinuity from the wafer level to the ring level; and 3) electrical discontinuity due to RF coupling termination at the wafer edge. Because of these three discontinuities, the plasma sheath profile at the wafer edge becomes curved, resulting in off-normal incidence of ions (FIGURE 5). Consequently, for certain processes, the trench profile at the wafer edge may tilt in the direction of ion incidence, as shown in FIGURE 6a. One innovation for improving the edge profile is our advanced edge control (AEC) kit. The AEC kit alleviates electrical discontinuity by optimizing the cathode to extend uniform RF coupling beyond the edge of the wafer. Sheath bending is thereby corrected and the ions are normally incident (i.e., are no longer tilted), resulting in straighter trench profiles (FIGURE 6b).

FIGURE 6. STI profiles at 3mm from the wafer edge (147mm radius) (a) without AEC kit and (b) with AEC kit (processes were not fully optimized).

Mainstream commercial inductively coupled plasma (ICP) sources utilize planar or helical coil geometries [14]. For either type, radial distribution of the electromagnetic fields are not homogenous, leading to non-uniformities in plasma generation that in turn introduce non-uniformity in the etching rate across the wafer. As plasma uniformity is mainly related to the plasma source and gas delivery, tweaking the source coil configurations and gas delivery systems can help improve uniformity. This is achieved in our silicon etcher's source by using two helical coils where both the current ratio between the coils can be independently controlled and the phase between the currents can be tuned (FIGURE 7a) [15,16]. When the inner and outer coil currents are in phase, the characteristic donut shape in the etch rate distribution across the wafer is observed (FIGURE 7b). Note that varying the current ratio improves the uniformity slightly, but not significantly enough to be production worthy. When the inner and outer currents are out of phase by 180 degrees, etch rate distribution can be tuned from being edge-high to center-high (FIGURE 7c). By optimizing the inner-to-outer coil current ratio, a very uniform etch rate can be achieved.

FIGURE 7. Uniformity improvement with reverse source (a) schematic of Mesa source with inner and outer coils, (b) the etching rate distribution with the inner/outer coil currents in phase, and (c) the etching rate distribution with the inner/outer coil currents out of phase by 180 degrees. Arrows in (b) and (c) indicate increased inner/outer source current ratio.

Pattern collapse

Pattern collapse becomes a significant problem as STI line widths shrink and aspect ratios increase. STI lines may bend when an external force is applied, and the bending distance depends on the magnitude of the force and the stiffness of the line. The external forces might arise from electrical charges, mechanical movement, or capillary forces during wet cleaning. The multiplicity in the origins of the force makes the pattern collapse issue complicated and each case different. In the case where electrostatic forces dominate, plasma etching processes must be tuned to prevent charging. For mechanical shocks, wafer transfer procedures must be adjusted. If the pattern collapse derives from wet cleaning, an alternative cleaning solution or method (e.g. dry cleaning) must be adopted. In summary, external forces should be eliminated or minimized.

From the point of view of line stiffness, the line profile is also important to prevent line sticking. Senturia [17] showed that the stiffness of a line is a function of the material properties and the pattern geometries:

Where, k is the line stiffness, E is the Young's modulus, and AR is the aspect ratio of the line. The high Young's modulus of silicon makes it less subject to pattern collapse than the resist in photo lithography; before the sub-20nm era, line collapse was not a significant issue for STI etching. However, as shown in Eq. 1, the stiffness of a line is inversely proportional to the cube of the line aspect ratio. Thus, as the aspect ratio increases, the propensity for silicon lines to stick to each other increases even under constant external force magnitudes. Moreover, any profile defect, such as local bowing, could significantly decrease the line stiffness. And if the device design and the integration process allow, a tapered line profile might be preferred to prevent line collapse as the feature sizes shrink further.

Conclusion

STI etching has become very challenging in the sub-20nm era. Four major challenges were reviewed in this paper. Intra-cell depth loading could be managed with advanced process tuning, and three general process development rules for avoiding this issue were provided. A combined solution of hardware innovation and process tuning achieved across-wafer etching rate uniformity and uniformity control over profiles near the wafer edge. Sub-20nm node STI features are susceptible to pattern collapse; aside from eliminating or minimizing external forces, a reasonable STI profile should be obtained if bowing is avoided during the plasma etching process.

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Solid State Technology | Volume 56 | Issue 4 | June 2013