Statistical variation monitoring for production control

06/03/2013

TIMOTHY TURNER, College of Nanoscale Science & Engineering (CNSE), Albany, NY.

The sources of parametric variation are reviewed, with an eye on why these issues become worse as the technology is scaled and how this variation can be monitored and controlled.

As semiconductor technologies become smaller, the processes become more complex. This is a long established trend in the semiconductor industry. Unfortunately, it is not a linear relationship. The relationship is exponential. As we approach the limits of scaling, this exponential effect becomes nearly vertical. In his presentation "Beyond 28nm: New Frontiers and Innovations in Design for Manufacturability at the limits of the scaling roadmap," Luigi Capodieci [1] describes the significant increases in technology required to move from 28 to 20nm. He describes multiple new layers, double patterning and extensive error corrections and review procedures required to achieve the new scaling targets.

Monitoring and controlling the variation in a semiconductor process during production has long been the task of parametric testing. These are electrical tests performed on semiconductor wafers at the end of the production cycle. The parametric variation increases with the square of the number of sources of the variation. Thus, the parametric testing function is stretched even more than the process by the exponential increase in complexity.

In chapter 1 of the book "Low Power Variation-Tolerant Design for Nanometer Silicon" [2] A. Bansai and R. Rao point out sources of manufacturing variation, intrinsic variation and design variation. Design variation is not an issue for parametric test. Process variation has long been the focus of parametric test. However, this focus has long been on lot-to-lot variation, wafer to wafer variation within a lot and site-to-site variation across a wafer (typically center-to-edge variation). Unfortunately, at the nanoscale level, transistor-to-transistor or metal line-to-metal line variation is also a concern.

This is a significant departure from historic techniques for parametric test where the structures tested were typically one transistor or one via. To address the element to element variation, statistical structures tabulating the variation of hundreds or thousands of circuit elements is necessary.

Since about the 2 micron generation, parametric test has been limited to scribe lanes. At that technology node, single elements were all that would fit in the scribe lanes. Now, it is possible to place thousands of transistors in a scribe lane structure beside a die that might hold billions of transistors.

FIGURE 1. Charge trapped in the gate oxide modulates the channel current. Shown are two traps: 1 and 2. The peak magnitude of the noise is the sum of all traps.

Statistical test structures are required to monitor the changes in variation that are critical to designers. Consider the impact of Random Telegraph Noise. This issue was first identified as a future issue back in the 1980's. Van der Zeil [3] pointed out that Random Telegraph Noise (RTN) was proportional to the inverse of the size of the gate area on the transistor. RTN is caused by traps in the gate dielectric. As shown in FIGURE 1, trapped charge in the dielectric modulates both the number of carriers and the mobility of the carriers under the gate [4]. Large transistors with perhaps hundreds of trap sites per transistor show little impact when one trap fills or emits. At the 45nm node, Realov and Shepard [5] showed that almost half of the transistors contained no traps, but the rest contained as many as five traps per transistor. The probability of holding one or more traps decreased with the gate area, but with a billion transistors on a die, 0.1% would leave 1 million transistors with multiple traps per die.

With 45nm transistors, a single trap caused on the order of a 10% change in the channel current at the worst case bias [5].

Realov and Shepard also showed that van der Zeil was an optimist concerning the scaling implications. They showed that a reduction in channel length could not be compensated by an increase in channel width (FIGURE 2). With identical effective gate dielectric areas (effective length times effective width), the shorter length transistor would always show a higher amplitude for the noise.

FIGURE 2. RTN increases with the inverse of the gate area. Realov and Sheppard showed that below 45nm, this increase can be greater, more a function of length than area.

Further adding to the problem is the reduction in signal levels required to scale the gate dielectric voltage when the transistor is scaled. The trap is a fixed charge. Its impact is set by that charge. As we lower the signal level, we increase the percent impact of that charge.

Waltl, Wagner, Reisinger, Rott and Grasser [6] characterized the traps using a technique called Time Dependent Defect Spectroscopy (TDDS). This technique uses a short (1ms) gate voltage pulse to fill the traps, then biases the channel so as to measure the emission of the traps. The traps are characterized by the voltage step when the trap emits and the time since the gate pulse was turned off when the trap emits. This was shown to be a repeatable characterization for each transistor, providing a characterization of the traps in that transistor. This technique allows not only the measurement of the number of transistors that show traps, but a further characterization of the traps.

TDDS can identify 1/f noise sources as well as RTN. When a large number of transistors are measured, a spectrum of the traps available at that site on the wafer is provided. This spectrum can be an important process control tool.

FIGURE 3. TDDS ??? Charge emitted from traps after a gate voltage pulse is removed. Multiple charge and discharge repetitions generate the probability clouds around different magnitude and time points [6].

For instance, Pobegen, Nelhieel and Grasser showed the impact of local hydrogen concentration on interface hole traps. This suggests that TDDS could be used to monitor the local hydrogen concentration across a wafer (FIGURE 3). Other issues such as radiation damage, charge damage and interface stress may be correlated with TDDS spectra.

FIGURE 4. Via Resistance Distribution for different via sizes (J. W. Sleight et. Al. [7])

Contact resistance is another statistically distributed function. As shown in FIGURE 4, Sleight et. Al. [7] observed that the contact resistance followed an analytical cone model due to variation in the bottom diameter, height and angle of a contact stud. If we now add the process changes projected by Capodieci [1] for 20nm technology, we may see the variation caused by stacking up to 4 via layers below metal 1 (FIGURE 5). The variation of each via layer will be a much more tightly distributed parameter than what results when 4 of these layers are stacked.

FIGURE 5. 20nm technology will require more process steps than previous technology. This will increase the variability in the process parametrics. (Capodieci[1])

Line Edge Roughness (LER) is another source of variation [8]. LER on a gate electrode can modify the local channel length resulting in a variation in the transistor's performance. Since this variation provides an effective variation in the transistors channel length and a shorter channel length provides a higher Random Telegraph Noise, LER will introduce still more variation in the RTN.

LER also impacts metal lines. In this case, the resistance of the line will always show the average line width. The metal line resistance is most important for long lines. Long lines tend to average out any line width variation making line resistance insensitive to LER. Unfortunately, linewidth variation correlates with line spacing variation. Line spacing will have a lifetime limited by the shortest space.

Measuring the leakage between two long lines is not an effective way to measure the variation in the line width. The best way to directly measure the variation is to measure the variation in the voltage required to induce a very low amount of leakage between a large number of shorter metal lines. This will provide the desired statistical variation in the line to line space.

Statistical variation is difficult to measure using traditional parametric test methods where each transistor is attached to four probe pads. Statistical variation measurements require the use of on-chip multiplexers and may be enhanced by on chip measurement techniques.

FIGURE 6. Array of Transistors for Characterization. For instance, the row and column addresses could be generated by two six bit counters allowing the independent characterization of 4096 transistors using only 8 probe pads (Vdsforce, Vdssense, Vgsforce, Vgssense, Vsub, Clock, Vcc, Gnd, Vsforce and Vssense). Adding an on chip A/D converter would decrease measurement time while reducing noise and adding only one serial data port.

On chip multiplexers using kelvin measurement techniques can build arrays of hundreds and even thousands of transistors, metal lines or vias accessed using only a few pads (FIGURE 6). A power supply, a pulse generator and a voltmeter or DAQ is all that is required to measure these arrays. An array of 500 transistors could be measured with as few as 4 probe pads.

On board A/D converters will accelerate the throughput of these tests, allowing parallel testing with few probe pads while the close space between the transistor and the instruments gives less measurement noise.

References

1. Luigi Capodieci, "Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap," http://www.isqed.org/English/Archives/2012/Presentations/Beyond_28_New_Frontiers_DFM_ISQED_ 2012.pdf.

2. S. Bhumia and S. Mukhopadhyay, editors, "Low power Variation Resistant Design for Nanometer Silicon, Springer, Chapter 1: Variations: Sources and Characterization," by A. Bansal and R. Rao.

3. A. Van der Zeil, Noise in Solid State Devices and Circuits, New York: Wiley, 1986.

4. K.K. Hong, P.K Ko, Chemming Hu and Yiu Cheng, Random Telegraph Noise of Deep Sub-Micrometer MOSFETs, 1990 IEEE 1741-3106/90/0200-0090.

5. S. Realov and K. Shepard, "Random telegraph noise in 45nm CMOS: Analysis Using an on-Chip Test and Measurement System," IEDM 10-624, 978-1-4244-7419-6/10/.

6. Michael Waltl, Paul-Jungen Wagner, Hans Reisinger, Karina Rott and Tibor Grasser, "Advanced Data Analysis Algorithms for the Time-Dependent Defect Spectroscopy of NBTI," Integrated Reliability Workshop, 2012 7.6-2.

7. J. W. Sleight, "Challenges and Opportunities for High Performance 32nm CMOS Technology," 2006 IEDM 1-4.

8. Asen Asenov, Savas Kaya and Andrew R. Brown, "Intrinsic Parameter Fluctuations in Decananometer MOSFETS Introduced by Gate Line Edge Roughness," IEEE Transactions on Electron Devices vol. 50 no. 5, May 2003.

TIMOTHY TURNER, is the Reliability Center Business Development Manager at the College of Nanoscale Science & Engineering (CNSE), Albany, NY. [email protected].

Solid State Technology | Volume 56 | Issue 4 | June 2013