Issue

The MEMS market has long been in a state of extreme fragmentation. Even now, according to a new report from France-based market research and consulting firm Yole Développement, MEMS devices are actively being produced by some 300 companies, 250 of which sell less than $20 million worth of products annually.

Worldwide silicon area wafer shipments rose another 4% in 2Q06 vs. the prior quarter to nearly 2000 million sq. inches (MSI), more proof that wafer suppliers are enjoying robust sales and heavy demand.

At the Symposium on VLSI Technology in June, SEMATECH reported on a new approach it has developed to meet ITRS requirements for low-standby power (LSTP) transistors for the 45nm technology generation.

In a bid to enhance the performance of microprocessors, the Semiconductor Research Corp. (SRC) recently said it has a plan to develop self-healing chips-i.e., chips that don’t fail, having been designed to diagnose when components wear out and heal themselves on the fly.

Researchers at the U. of Pennsylvania and St. Josephs U. are touting their work on chromophores, which when linked together enable transfer of electrical charges that exceed mobility in organic semiconductors by up to a factor of three, and hold promise for applications in displays and solar cells.

Atomic layer deposition (ALD) processes require vacuum conditions both for proper deposition and adequate purging of precursors from the chamber.

The IX-250 excimer laser micromachining system is a Class 1 industrial-grade workstation that can accommodate a variety of excimer lasers, offering 12 axes of motion, with 250mm×200mm travel (for processing 150mm wafers).

With the introduction of the immersion technique into deep-submicron patterning, the semiconductor industry will manage to keep up with the scaling roadmap using refraction-based lithography for another two, hopefully three generations before switching to the most likely successor, extreme ultraviolet (EUV) lithography.

Balancing the lifetime and residence time of radicals is critical to achieving acceptable radical oxidation growth rates and uniformities in large-batch reactors.

The requirements for the source/drain extensions of future devices are increasingly more demanding with respect to dopant activation, junction depth, and abruptness as semiconductor technology continues to scale [1].

As design rules have shrunk, the overlay of implant layers has become a problem [1].

Different performance and wafer-yield criteria apply to different types of integrated circuits, and the masks for those circuits may need to be optimized to achieve maximum value of production.