While recent industry roadmaps have shown many red brick walls ahead, mapmakers say they are confident that the industry will still be able to follow the track of Moore's Law for another 15 years.
NEC has cut standby current leakage at the 65nm node by 30–100× by using HfSiON as the high-k gate dielectric and a transistor structure optimized for Transmeta Corp.'s LongRun2 technology to dynamically adjust the body bias as well as the supply voltage.
New global guidelines and semiconductor industry targets for protecting the environment are compelling chipmakers to consider options for waste/effluent treatment and reduction.
The electrochemical etch-stop (ECES) technique is a popular method for bulk micromachining of a p-n junction silicon wafer in microelectromechanical (MEMS) applications because it has the ability to fabricate microstructures and membranes with precise thickness control.
The use of organosilicate glass (OSG) as a low-k dielectric in copper interconnects creates challenges in cleaning wafers after they have been through chemical mechanical planarization (CMP).
The emergence of equipment data acquisition (EDA) standards, such as the new Interface A standard, opens up the possibility of plug-and-play manufacturing tools with greater levels of automation in semiconductor fabs.
In the 1970s, Japanese IC manufacturers were trying to catch up to the US. In the 1980s, they took the lead and dominated DRAM while the US refocused on logic.
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