Issue



Table of Contents

Solid State Technology

Year 2004
Issue 8

DEPARTMENTS

Editorial


Moving (slowly) toward full automation

The global semiconductor industry is exhibiting many different signs of a maturing industry, and the current status of automated manufacturing is one of those signs.


World News


Business Trends and Worldwide Highlights


Tech News


Technology News


Compound Semiconductors


Optical interconnects promised by III-V on-silicon integration

The 2003 International Technology Roadmap for Semiconductors (ITRS) notes that monolithically integrated, low-cost light emitters, detectors, and modulators are interesting possible solutions for impending silicon CMOS interconnect challenges.


Feol


Exploiting design regularity foroptical RET lithography

Semiconductor lithography is facing a critical crossroads.


Product News


Product News


Perspectives


Testing new business models

Solid State Technology asked suppliers to discuss manufacturing process strategies in the current industry climate.


FEATURES

Cover Article


Topography control using sacrificial capping layers

Capping layers can protect porous low-k materials from subsequent processes.


Lithography


Optimized illumination settings extend ArF lithography to 65nm

The extension of 193nm ArF lithography to 65nm processes will be necessary because of delays and problems with 157nm tool deployment.


Metrology


A nonpenetrating 4PP measures USJ sheet resistance

A new method using elastic-material (EM) probes to form nonpenetrating contacts to the silicon surface to measure the four-point probe (4PP) sheet resistance of USJ source/drain structures is described.


Packaging Assembly


How buffer layers can provide stress management for wafer-level chip-scale packages

Wafer-level packaging (WLP) holds significant promise in enabling higher performance, smaller form factors, and cost savings in IC products, but the introduction of new materials in semiconductor manufacturing raises reliability considerations.


Device Engineering


An analytical look at vertical transistor structures

The combination of device enhancements, such as strained silicon configurations, SOI, and nonplanar transistor device structures, in conjunction with the current state-of-the art global efforts in high-k gate dielectrics, metal gate electrodes and elevated source/drain, offers a plethora of opportunities for IC manufacturers.


Cmp


Removing copper over low-k films using stress-free polishing

With the convergence of chemical mechanical planarization (CMP) and low-k dielectrics for copper dual-damascene interconnects at the 130nm technology node and below...


ASIA-PACIFIC-SUPPLEMENT

Departments


News


Features


How Taiwan's foundries have closed the gap with IDMs

In less than a decade, the dynamics between Taiwan's large silicon foundry base and leading integrated device manufacturers (IDM) have shifted dramatically.


Features


Taiwan becomes driving force in single-wafer technology

Adoption of single-wafer processing technology for semiconductor manufacturing continues to increase worldwide, but the Asia-Pacific region — particularly Taiwan — is outpacing the overall global growth rate.


Features


What's next for Taiwan's IC industry?

Faced with the threat of mainland China's growing silicon foundry and chip manufacturing segments as well as its low-cost labor, Taiwan's IC industry is under pressure to transform itself into a high value-added, design-driven industry in order to remain competitive in global markets.


Features


What's still holding back China's huge fabless potential

The industry's current "up" cycle has been notable because of its strength despite the lack of a new killer application; the cycle has been buoyed instead by many minor new applications and in large part by the existence of a "killer geography" — China.


Features


Supporting Asia's rapid expansion raises stakes for fab suppliers

When it comes to Asia, semiconductor industry suppliers face a daunting challenge in the current strong recovery cycle.