Issue

Table of Contents Solid State Technology Year 2004 Issue 7	DEPARTMENTS Editorial New look for process tools? As the industry congregates for Semicon West this year, some changes are in the wind. World News World News Tech News Technology News Feol Sub-1nm EOT scaling for high-k/metal-gate stacks The aggressive scaling of advanced devices has necessitated the search for a suitable high-k gate dielectric. Product News Product News Semicon West 2004 Perspectives Has outsourcing changed the landscape? Solid State Technology asked executives to comment on semiconductor manufacturing models.

FEATURES Mems Addressing sidewall roughness using dry etching silicon and SiO₂ The common element in micro-optical electromechanical systems (MOEMS) is the requirement to manipulate the optical signal ??? light ??? via surface reflection or gratings. Deposition Nonlinear models used to address epi layer uniformity Engineers in semiconductor fabs depend on trial-and-error experimentation to improve thickness uniformity, a quality measurement for epitaxial layers grown by CVD. Wafer Cleaning What's driving the new momentum behind cryogenic aerosols Whether the particle defects are random or due to process excursions, their removal from wafer surfaces is becoming more difficult without damaging or altering the material properties of surrounding structures. Software Analyzing strained-silicon options for stress-engineering transistors Future silicon technology will depend on locally strained silicon channels to squeeze higher currents from each process node. Compound Semiconductors New processes allow InP HBTs to top 150GHz Standard compound-semiconductor manufacturing techniques, such as lift-off contact metallization and unique epitaxial structures, while viable for low transistor-count applications, have process yield limitations that prevent increased integration of these submicron devices into ever-smaller circuit dimensions. Waste Effluent Treatment The many options for managing CMP wastewater Waste streams from CMP can vary greatly depending upon a wide variety of factors in wafer processing, and one "right" solution for treatment of CMP wastewater may never exist. Materials Integrating a nonporous low-k (k = 2.2) film Several low-k (≤2.7) dielectric films will be examined in view of critically important properties required for IC integration, reliability, and IC packaging. Etch Mechanisms for improving sub-90nm etch processing The challenges for etch processing at sub-90nm include tighter critical dimension uniformity, and higher selectivity to maintain smooth sidewalls and control silicon recess. Automation Robotics Approaching tool automation with an application program interface standard Deploying automation software and tool interfaces for 300mm wafer fabs becomes more complex as Semi standards evolve and expand. Gas Handling Model-based solution for multigas mass flow control with pressure insensitivity Relentless advances in semiconductor manufacturing have placed extreme performance demands on gas delivery systems. Photoresists Exploring the needs and tradeoffs for immersion resist topcoating Immersion lithography has quickly become the leading candidate to extending 193nm scanners to the 45nm process node. Metrology Etch and CMP process control using in-line AFM As aspect ratios become higher, features become smaller, and requirements for planarity tighten, atomic force microscopy has begun to replace profilometry for topographic measurements such as trench and via depths, step height, and micro-planarity measurements, both in development and in production. Contamination Control Fabs can ride through voltage sags with power-quality targets Interruptions and brief disturbances in utility power during semiconductor manufacturing can result in significant loss of revenue, productivity, production yields, and product quality.

ATTENDEES-CHOICE-AWARDS Wafer Processing San Francisco — Decision roller derby: multiple paths down the Roadmap A showcase for solutions has never been more in need now that divergent paths down the industry roadmap have evolved. Wafer Processing WAFER PROCESSING — PRODUCTS Final Manufacturing San Jose — Packaging, assembly and test drive competitive solutions into the final manufacturing space Cheaper, faster, smaller, better—all of the good things being targeted by wafer fabs and Moore's Law of device shrinks are also squarely in the scope of final manufacturing and test technologies. Final Manufacturing FINAL MANUFACTURING — PRODUCTS

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