Table of Contents
Solid State Technology
Year 2004 Issue 3
| DEPARTMENTS
Editorial Dual routes for R&D may be best
With research dollars being cut back by both the US government and private companies (see "Will the US lose its lead in research?" Solid State Technology, January 2004, p. 12), it would be wise to tune the funding model to gain maximum effectiveness.
World News World News
Tech News Technology News
Feol A new definition of
Until recently, mask data preparation (MDP; including fracturing) was considered a commodity service conducted after tape-out that facilitated the transition of the design data into a maskwriting format for mask manufacturing.
Interconnect Looking forward to 65nm: Nonporous low-k dielectrics
In the early 1990s, when the search started for low-k dielectrics to provide lower capacitance and improve signal integrity by reducing crosstalk between adjacent lines, process engineers wanted low-k materials to be the direct replacement of PECVD oxide (k ≈ 4).
Tap ITRS: Increasing complexitycreates packaging challenges
The 2003 edition of the International Technology Roadmap for Semiconductors (ITRS), made available in December (http://public.itrs.net), highlighted many challenges related to system-in-package issues and the increasing complexity of semiconductor products, as well as the growing interrelated nature of semiconductor design and manufacturing flows.
Product News Product News
Perspectives Using collaboration to tame Cu/low k
Solid State Technology asked industry experts how collaboration was enabling progress on Cu/low-k integration.
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FEATURES
Cover Article Coming clean about
Shrinking feature sizes are making devices increasingly vulnerable to gas-phase contamination.
Mems Microfabrication process enables 3D metal microdevices
Overcoming the limitations of MEMS technology based on planar silicon techniques can be achieved by sequential deposition of high-conductivity metals. This approach enables the design of different structures, including high-Q RF devices, on the same substrate without the need for manual processing.
Deposition High-performance SiGe pHMOS using reduced-pressure CVD
A high-performance SiGe p-type metal-oxide-semiconductor heterostructure field effect transistor (pMOS-HFET or pHMOS) has been developed using a well-controlled boron delta-doping and SiGe/Si heterostructure epitaxial process with reduced-pressure chemical vapor deposition.
Materials Temporary bonding technology improves thin wafer handling
The processing of compound semiconductors often requires back-thinning of the processed wafers or backside lithography.
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SEMICON-EUROPA2004
Preview Semicon Europa 2004 Preview
April 19-23, Munich, Germany
Products Semicon Europa2004 Products
Semicon Europa showcases semiconductor equipment, materials, and services in Europe. Following are some of the new products that will be exhibited at the show.
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