Table of Contents
Solid State Technology
Year 2002
Issue 11
 | DEPARTMENTS
Editorial
What will get the monkey off our back?
Is the semiconductor industry stuck in a rut because there is no Killer Ap on the horizon?
Letters
Modular fab design challenges status quo
I agree almost 100% with your excellent September editorial, "Can fabs be built twice as fast for half the cost?" I wonder, however, whether a nascent semiconductor-manufacturing country like China would be willing or able to implement an idea as novel as modular fab design.
World News
Chip sales rise, equipment orders drop in August
Chip sales increased month-to-month and year-to-year in August, supporting thoughts of a broad-based recovery, according to the Semiconductor Industry Association (SIA).
Tech News
MEMS and SAWs 'zipped' into packages
Ziptronix, Research Triangle Park, NC, has adapted its proprietary materials bonding technology for dissimilar semiconductor materials to a wafer-scale method for encapsulating surface sensitive devices, including MEMS and SAW filters.
Asiafocus
Officials hope SoC plan will push IDMs toward new foundry strategy*
(Extracts from an interview with Hidetaka Fukuda, director of the IT Industry Division, Commerce and Information Policy Bureau, of Japan's Ministry of Economy, Trade, and Industry [METI], by Hiroshi Asakura, associate editor of Nikkei Microdevices, regarding Japan's Advanced SoC [system-on-chip] Platform Corp. [ASPLA] plan)
Industry Insights
Time for a communal 300mm CMP apps lab
IC manufacturers made it clear at the CMP-MIC meeting in February 2002 that the high cost of CMP slurry in the fab and the desire to have multiple viable slurry suppliers were issues that needed to be tackled.
|
FEATURES
Cover Article
Using neural networks for intelligent plasma etch process control
Run-to-run control — the ability to guide a process based on process results rather than just tool settings — has the greatest potential impact on wafer processing productivity.
Lithography
Using phase shifting to extend 248nm litho beyond the 50nm gate process
overview
Using a dark-field AltPSM double-exposure process, it is possible to print gates at 50nm. By optimizing some key parameters, 248nm and 193nm lithography can be used to print gates as small as 25nm [1].
Materials
Cold-wall UHV-CVD for Si-SiGe(C) epitaxial thin films
overview
Increasingly, SiGe BiCMOS is needed to fabricate high-performance ICs. Deposition of a suitable selective SiGe epitaxialmaterial has always been a somewhat difficult process to control.Now, through gas-flow ratio control on a cold-wall UHV-CVD system, a group of engineers has achieved SiGe deposition selectivity onsilicon vs. SiO2and Si3N4, over a wide range of film compositions.
Gases Gas Flow
Photolithography advances push purge-gas purification
overviewProcess success with advanced lithography involves a wide range of factors, including a tool's ambient environment. Use of shorter wavelengths of light has increased the potential for photon-induced reactions creating byproducts that deposit on lenses and hamper performance, dictating the need for extremely clean lens purge gases.
Cmp
Slurryless CMP enables next-generation direct polish STI
overview
As device geometries continue to shrink, planarity requirements for shallow trench isolation chemical mechanical planarization are becoming increasingly stringent.
| 
