Issue

Chipmaking has been able to track Moore's "Law" since the 1960s because of the coordinated efforts of every part of the infrastructure, from wafermaking to patterning and lithography, and on to final test.

Photomask specifications for advanced KrF and ArF lithography tools require improvements in both glass substrate quality and coating development. These improvements are being driven by several factors, including the demanding CD requirements of advanced photomasks and the increased use of phase-shift masks (PSMs).

IC manufacturers switching over to low-k interlevel dielectric (ILD) materials from SiO2 and fluorinated silica glass (FSG) have encountered a variety of problems, including delamination, peeling, and cracking.

Solid State Technology asked an analyst and an IC manufacturer for their take on the current foundry business model.

Electroplating sub-100nm Cu interconnects using large electrolyte baths faces limitations in the area of defect control repeatability and gap-fill consistency. A modular plating cell design with an independent electrolyte circulation loop supports a multistep plating process with different chemistries in different cells, enabling approaches to meet both gap fill and film planarization for sub-100nm Cu metallization.

The rapid scaling requirements projected by the International Technology Roadmap for Semiconductors (ITRS) pose several key challenges that are very much dependent on device application. Though progress has been made in the areas of high-k gate dielectrics and metal gate systems, several issues remain — particularly scaling, threshold voltage control, and mobility degradation — and it is critical that the industry focus efforts to resolve them.

Chemical mechanical planarization has the ability to planarize interlayer dielectric layers, tungsten layers, and even metal layers of aluminum and copper to adequately meet current industry needs. However, its compatibility with fragile low-k materials used in copper dual damascene processes is questionable.

Traditionally, the shrink of semiconductor IC devices has been enabled primarily through the reduction of the exposure wavelength. Optical lithography capabilities, however, have been extended to the sub-100nm regime through heavy utilization of reticle-based resolution enhancement techniques.

Increasing use of very thin, flexible wafers for IC manufacturing brings with it extremely challenging automated handling problems. Individually, vacuum- or Bernoulli-based end-effectors cannot solve all problems. But the combination of these two techniques in one end-effector design provides effective automated handling for several emerging applications.

The front-opening unified pod is synonymous with 300mm wafer handling and contamination control. However, simple intuitive purging of these pods apparently does not provide wafer cleanliness compatible with high yields. Rigorous simulation with computational fluid dynamic software shows just how pod purging can be improved.

Among transistor manufacturers, perhaps the main measure of technical excellence is RDSON, the resistance of the transistor in its on state. This value needs to be as low as possible to improve current carrying capability, and to minimize power consumption. There are multiple ways of reducing RDSON: thick interconnect layers, smaller pitch — that also benefits die size and cost — and thinner wafers.

Laser micromachining is just beginning to be used in semiconductor manufacturing. Some of the more applicable areas are found in assembly and packaging. As the benefits become more apparent for this arena, laser processing will undoubtedly replace traditional mechanical and chemical techniques.