Issue

In recent times, the semiconductor process tool industry has viewed China as the one shining light in a very gloomy market. Limitations on advanced tools for China appear to be rapidly being relaxed or ignored while new foundries and fabs there gear up to compete in the world semiconductor market.

The model begins with a geometric representation of the equipment to be analyzed.

Low-temperature (<500°C) formation of electrodes with low contact resistance is one of the key technical challenges in fabricating advanced devices with small features — particularly for conventional lamp-based RTP systems.

The industry-wide struggles to integrate copper low-k processes with the rest of the semiconductor manufacturing flow have been thoroughly documented [1].

For the first time, attendees at the Semicon West exhibition and conference in July got to choose the best products in three different categories as Solid State Technology (SST) debuted the first annual Attendees' Choice Awards at the show.

Solid State Technology asked industry automation professionals to discuss what is needed to resolve equipment-to-factory integration issues.

To meet the needs of customers and manufacturing partners, IC makers must get new products to market quicker, support shorter customer cancellation windows, and meet the complexities of multicompany joint ventures.

LSI Logic and INFICON have worked together to develop and integrate e-Diagnostics capabilities over six-to-nine months at the LSI Logic facility in Gresham, OR.

Backside defects have been largely ignored for several reasons, including the lack of suitable equipment and methods for backside inspection and the lack of awareness about the impact of backside defects on semiconductor manufacturing, particularly on yield [1–4]; yield improvement was never directly correlated to backside defect reduction in any of these references.

The future of microelectronics and nanotechnology are intimately tied together. The smallest feature sizes on today's ICs are already falling below 50nm.

As Moore's Law continues to shrink device features, the rapidly increasing volume of transistors/chip creates a constant rise in the pin count/chip.