Issue

Looking back, it's easy to recall that the huge "killer" applications for electronics that led to booms in the semiconductor industry were obvious. But in the early phases, it wasn't always that easy to predict that something would turn out to be a giant winner, like, in their time, transistor radios, calculators, color TVs, VCRs, and PCs.

IC manufacturers face a number of economic pressures today, not the least of which is the high cost of transitioning to tools with shorter wavelengths or higher numerical apertures. This, in turn, challenges lithographers to maximize the life of present-generation tool sets.

The industry's trend to more device structures stacked on a die, increasingly including copper interconnects and low-k dielectrics, has forced the need to develop techniques that will let us see, measure, and ultimately control these structures. new structures.

Solid State Technology asked industry experts for their views on the unique challenges and opportunities in the MEMS-manufacturing arena.

The impact of the semiconductor integrated circuit (IC) on modern life is hard to overestimate. From computers to communication, entertainment to education, the growth of electronics technology, fueled by advances in semiconductor chips, has been phenomenal.

Control of feature dimension is so crucial to producing ICs that the metrology step is routinely referred to as a critical dimension (CD) measurement. Manufacturing ICs with faster clock speeds requires controlled transistor gate length variation as well as interconnect structure control. So, a CD measurement can be either a linewidth or a contact-via diameter or area.

This technique detected slightly undersized contacts directly corresponding to the coordinates of the repeating wafer defects, yet these same defects had not been detected by standard reticle inspection.

To achieve production at sub-100nm device targets, a thinner (<2000Å) imaging layer with improved etch resistance will be required to obtain robust manufacturing processes.

As semiconductor manufacturing continues to follow Moore's Law, junction annealing has been forced to evolve to ever-shorter times and higher temperatures to limit transient enhanced diffusion and improve dopant activation levels.

Similar to those processes used by the large integrated device makers for high-volume CMOS products, the basic sequence of thin film deposition, photolithography, and etch is repeated many times to make a finished MEMS device.

At the 2002 IITC Conference, the authors reported a novel ALD-WN_xC_y process developed at ASM Microchemistry Ltd. for a diffusion barrier application using the Pulsar 2000 and 3000 ALCVD reactors [3].

As IC technology continues to grow, there will be an increasing need for engineered substrates tailored for specific applications.

As device dimensions continue to shrink, the lateral offset of the dopant due to shadowing effects becomes increasingly large relative to the size of the implanted well. This leads to variations in device and isolation performance as a function of feature orientation on the wafer.

Point-of-use (POU) abatement is often used to minimize the overall environmental, health and safety impacts of various semiconductor processes, including deposition and etch.

From a comparison of a conventional multitank, HF-last process to a single-step, in situ HF-last process, we have found that dilute chemicals and in situ HF and drying are key factors in cleaning wafers with submicron critical dimensions.

Visitors to the wafer-processing segment of Semicon West in San Francisco's Moscone Center will see a wide array of innovative products, allowing smaller features to be made with higher throughput and fewer defects.

Seasoned attendees of Semicon shows, particularly Semicon West with its split venue, know that a good plan of attack can increase your effectiveness on the exhibit floor.