Issue

Successfully making high-performance, leading-edge integrated circuits has probably become the highest form of manufacturing art ever.

It is clear that optical lithography will be used for IC production for the rest of this decade, but which optical technology will be used at each step of this journey is not. Progress with 248nm resists and reticle enhancement techniques has kept this wavelength in production far longer than most thought possible.

Why can't the industry make a solid film with k = 2.2, a Young's modulus (E) as high as 10GPa, and leakage current as low as 1x10^-10A/cm² in combination? The answer is: Three simple golden rules for making good low-k materials have been violated.

Only a few years ago, wafer-level packaging entered the scene because it solved some of the dire needs in packaging, particularly the natural progression of chip scale packages (CSP), by moving conventional backend processing into the frontend.

Solid State Technology asked industry experts to provide insight on reducing the impact of rising mask costs.

As the industry continues to scale devices to meet the various system-on-a-chip applications in the future, several types of transistor designs from planar and vertical single-gate, double-gate, and multigate devices are emerging, as are several options in silicon starting material (bulk CZ, epi, blanket SOI, and selective/patterned SOI wafers).

There is an immediate need for reduced gate leakage/higher capacitance gate stacks for stand-by low power applications. For high-performance applications, where leakage is less of a restraining factor, the motivation for the introduction of high-k dielectrics predominantly comes from the manufacturability difficulties of sub-1.0nm SiO₂-based dielectric layers.

The use of aqueous-based topside antireflective coatings (TARCs) for the purpose of improving CD control is a common photolithographic process. The benefits of the CD control however, can be negated by yield losses due to the formation of defects in the spin-on application of the TARC.

Maintaining constant line or sheet resistance across the wafer requires greater control of remaining copper thickness during the CMP process. Incorporating an in situ thickness sensor into the CMP process has yielded information not previously available — the actual evolution of the copper film thickness profile during polishing.

Germane gas is increasingly called for as a deposition reactant in wafer processing applications needing silicon germanium layers. Because this gas is a flammable, toxic, colorless gas reactive with oxidizers and halogens, its use in wafer fabs demands packaging that can ensure safe and environmentally friendly handling. Specific tests have analyzed these issues, particularly any potential for deflagration, when germane is packaged in a subatmospheric delivery system.

Within a wafer fab, a high percentage of systems use a vacuum or controlled atmosphere for deposition and other process steps. The passing of wafers into and out of these systems via loadlocks becomes a significant portion of overall wafer handling.

Overall equipment effectiveness has become an industry maxim closely associated with successful production. Yet, proper determination of this metric can be done at too high a level, failing to uncover real-life root causes. Achieving comprehensive data requires a four-step closed-loop process that starts with a reporting system, allows ongoing measurement and data mining, and provides for periodic studies.