Issue

It is widely believed that the Web will change our world in ways that so far are hard to predict. History has shown that dramatic changes occur in society not just as a result of inventions such as the printing press, telephone, and television, but even from the rise of developments such as roads, cities, and money.

Global chip sales reached $12.5 billion in December, a 2.3% drop from the $12.8 billion in revenue reported in November, according to the Semiconductor Industry Association (SIA), San Jose, CA.

On the worldwide list of 300mm fabs, Trecenti Technologies, Hitachinaka, Japan, may seem like just another advanced foundry. However, it is fundamentally different from other 300mm fabs.

As the industry continues to scale devices to meet the various system-on-a-chip (SoC) applications in the future, several types of transistor designs from planar to vertical single-gate (SG), double-.gate (DG), and multigate (MG) are emerging as are several options in silicon starting material (bulk CZ, Epi, blanket SOI, and selective/patterned SOI wafers) [1].

In 1993, two-thirds of the leading experts in IC intermetal dielectrics (IMD) expected that IMDs with k<3 would be used at the 0.35µm technology node, and one-third projected their first use at 0.25µm.

After reading through a recent barrage of new package-design announcements, I queried a few experts about package proliferation and the kinds of engineering and process capability challenges, perhaps stresses, that this proliferation is putting on the semiconductor industry.

Laser Pattern Generator

Recently, Solid State Technology asked several key industry executives: How do you perceive advanced process control (APC) developing (and being funded) in wafer fabs?

At the 130nm technology node, the introduction of 193nm resists has significantly increased etching challenges due to poor resist selectivity, a problem compounded by much thinner resist layers required to overcome depth of focus limitations.

It is not uncommon in wafer fabs to use one ion implanter for sequentially implanting multiple elements. This is effective, however, only if the potential for cross contamination is painstakingly controlled and monitored, particularly with phosphorus.

With damascene processing gaining acceptance in high-volume IC manufacturing, reliable analysis of copper plating baths is increasingly important. Cyclic voltammetric stripping has shown that it is an accurate and precise method for the control of the organic additives.

The adoption of silicon-on-insulator (SOI) wafers is clearly part of the future of advanced semiconductor manufacturing, particularly in extending planar CMOS technology beyond sub-50nm gates.

Launched in 1975, Semicon Europa showcases semiconductor equipment, materials, and services in Europe.

One part of successful wafer-level packaging is the need for integrating passive components with IC fabrication, rather than fabricating them separately for integration during conventional assembly and packaging.

The autodoping behavior of arsenic and boron in an epitaxial layer is strongly dependent on epitaxial process conditions. It is shown that autodoping could be minimized for both elements simultaneously by using low temperature (900°C) and low pressure (15 torr), at least during the initial phase of epitaxial growth.