Issue

A lot is riding on how well the industry executes a shift from 200mm to 300mm (12-in.) wafers. A smooth and rapid transition will mean big payoffs for a number of hardworking players.

Semi says equipment orders rising more slowly; Nine join with ASML on 157nm litho; Companies join forces on SOI smoothing process ...

Update on process-induced damage problems; Industry-leading flip-chip PBGA package; Role of e-connectivity applied to wafer fabs debated; FSI, Dow team up on low-k process

Sony, Fuji to hike capacity; Ushio and Komatsu enter excimer joint venture; Mitsubishi to boost investment 50%; NEC, Fujitsu may follow suit; Toshiba and others create next-level wafer equipment

SiGe technology is enabling silicon-based ICs to penetrate the rapidly growing market for wide bandwidth and wireless telecommunications.

Optical 3D profiler catalog from Veeco, Tucson, AZ; Supply chain web site from Scott Specialty Gases, Plumsteadville, PA; IC production tool brochure from ASM International, Bilthoven, The Netherlands; Heated vacuum valve brochure from MKS Instruments Inc., Vacuum Products Group, Boulder, CO.

A special report by the editors of Solid State Technology, Microlithography World, and WaferNews

Planar CMOS transistors on bulk silicon wafers are expected to reach their limits at gate sizes of about 50nm in 2005-06. Many of the process and materials constraints that combine to force this changein technology path are relaxed or removed for CMOS devices fabricated on SOI wafers. This article outlines the principal issues limiting junction formation for sub-100nm CMOS on bulk silicon and presents an alternative roadmap using SOI wafers.

A variable-speed vacuum system, using compact dry pumps, provides a production-worthy alternative to traditional methods of chamber pressure control for aluminum etch and LPCVD nitride deposition. Application to a single-wafer metal-etch tool allowed the elimination of a throttle valve close to the process chamber, thereby removing one source of contamination and tool downtime.

From the "red brick wall" of processing uncertainties as we strive to remain on the track of Moore's Law, some of the trickiest and most uncertain challenges are emerging. Consider, for example: the current and forecast state of optical lithography; two- and three-dimensional dopant profile spatial resolution needs ...

In 300mm wafer fabs, the transport wafer carrier will play a vital role in manufacturing success. Because of this role, it has become increasingly important to quantitatively test and measure wafer carrier performance. The wafer carrier architecture of choice for 300mm is the front opening unified pod or FOUP.

It is commonly accepted that optical lithography, including 157nm wavelength exposure, will enable manufacturing at the 70nm node. Translating the industry's official roadmap to an exposure tool roadmap, it is obvious that new wavelengths and optics with extremely high numerical aperture will be necessary.

PEB temperature is critical during the processing of chemically amplified 248nm (and below) photoresists. Variations in temperature directly affect CDs of final resist patterns. Many other process parameters can also influence CDs, however.

A major roadblock to single-wafer cleaning has been the lack of a fast, high-performance watermark-free drying technique. Now, IMEC engineers have developed two novel techniques that solve this problem. Both show excellent particle-addition control and high particle removal efficiency.

Thin film head manufacturers have leveraged equipment designed for IC fabrication, and this article reviews the impact on equipment design of the similarities and significant differences between the two types of products. A discussion of how various types of IC equipment were modified for the production of GMR thin film heads follows.

Yield management in the semiconductor industry has always focused on causal relationships between yield loss — or yield limitations — and the process. These have been the limitations inflicted by nonoptimized films, tool problems, and device design. For a new device, the goal of the analysis has been to move up the classic learning curve as quickly as possible to stabilize and maximize yields.