Issue

Canon brings big company muscle to the SOI market with yet another technology; Asia Briefs; Japanese firms band together for green standards; NEC reorganizes DRAM, LCD production...

With chipmakers starting to show some signs of serious interest in silicon-on-insulator wafers, Canon, Tokyo, Japan, is stepping up its efforts to promote its alternative bonded-wafer technology, using water jet cutters and hydrogen annealing instead of CMP.

A listing of industry events from June to November 2001.

Putting a whole system on a chip is a neat concept that has turned out to be tougher than it looked at first. But the trend is clear: SOC is the way of the future. With the capability of putting many millions of devices onto a single chip, it is very enticing to try to cram as much of a system as possible onto one large die.

WORLDWIDE HIGHLIGHTS; USA; JAPAN; EUROPE; ASIA PACIFIC

Floating 3-D display seemingly out of sci-fi; A tunable slurry for copper damascene CMP; 3-D packages require less handling, spac...

The bright promise for many new materials entering chipmaking is tempered by more realism as research progresses. The latest science coming out of this work drew intense interest — and some debate — at the Materials Research Society Spring Meeting in San Francisco. Key topics in wafer processing included low-k dielectrics, CMP processes, and ion implantation.

While the chipmaking and equipment industries face a downturn, European companies are betting on their marketplace diversity to aid them in weathering the storm. Numbers reflect what analysts are speculating: Europe is rich with niche companies that are surviving the downturn by keeping on top of the in-demand markets.

Semiconductor manufacturers primarily use polished silicon wafers (PW) and epitaxial silicon wafers (epi) as the starting material in IC fabrication.

This year's Semicon West tackles the industry's evolving technology challenges through comprehensive program offerings. Whether it's an introductory course on wafer fabs or a briefing on the International Technology Roadmap for Semiconductors, Semicon West 31st's annual conference promises to address the varied needs of professionals in the semiconductor industry.

Wafer surface and edge inspection; Automated CD measurement; Nanoindentation test system; Photoresist removal solvent; 300mm wafer carriers...

Current backend-of-the-line processes require significant volumes of semiaqueous solvents for removing post-ash residues. A joint study on reducing chemical consumption while maintaining process capability by FSI International and 1st Silicon found that batch spray processing with built-in recirculation could reduce chemical costs by more than 80%.

Low-energy boron implantation is a critical process for semiconductor doping today [1]. Decaborane has been shown to be an attractive alternative to monatomic boron for shallow junction formation. Motivated by the requirement for these ultra-shallow junctions, researchers have demonstrated the conventional application of decaborane beams.

Toshiba, TEL, and a new Japanese national project aim to come up with a better way to quickly turn out small volumes of complex systems chips at low cost, by rethinking the entire semiconductor production process.

Automation for 300mm fabs absolutely requires comprehensive attention to the interrelationships between the four levels of automation: FOUPs and wafer-handling automation, tool frontend automation, intrabay automation, and interbay automation.

A method for optimizing parameters to control CMP removal rate uniformity has been developed and tested. The design-of-experiment method was used to determine empirically the sensitivity of removal rate at various wafer radii using linear belt CMP tool parameters. The recipe was determined to achieve the most uniform final profile for a given incoming film thickness profile.

The density and type of defects in single-crystal silicon wafers are functions of the growth rate of the crystal and the temperature gradient at the liquid/solid interface during crystal growth. Different types of defects dominate in different ranges of the input variables, and it is possible to identify a process range that minimizes the defects.

A novel method for in situ depth and reflectivity measurements during dry etching is presented. The method is based on laser interferometry with a CCD chip as the detecting element. This allows for a process alignment to typical critical layout structures using optical markers.

Plasma etch processes can be tailored to address MEMS device fabrication challenges, including high aspect ratio structures in silicon, thin noble metal and piezoelectric structures, and optically active compound semiconductor devices.

This article examines techniques and theoretical modeling for determining the suitability — particularly "dry-down" behavior — of different types of materials for the construction of gas distribution systems in a semiconductor manufacturing facility.

A current generation of laser microchemical etching systems removes bulk silicon with several-micron resolution at a rate of 100,000?m3/sec. With no further steps, these systems leave behind perfect mirror-smooth surfaces. Furthermore, it is a 3-D direct write process.

A production-worthy, five-wafer annealing system using six stacked hotplates is proposed for low-temperature (100-450°C) applications such as Cu, Al, SOG, photoresist, and low-k dielectric annealing for 300mm wafers.

As the semiconductor industry moves to the 130nm process node and beyond, photomask manufacturing has fundamentally changed. Technologies such as phase shift masks (PSMs) and optical proximity correction (OPC) have become part of the standard lithography process and the photomask is moving from a commodity product to a value-added part of lithography.