Lithography

LITHOGRAPHY ARTICLES



HDD patterned media using jet-and-flash imprint lithography

09/04/2009 

This article from Molecular Imprints describes how te addition of patterned media to HDD disk fabrication presents a number of new challenges to magnetic media manufacturers, and how J-FIL systems and materials can provide the foundation for successful high-volume manufacturing.

MII's template replication system enables patterned media manufacturing

09/03/2009  Molecular Imprints CEO Mark Melliar-Smith tells SST how the company's new Perfecta TR1100 template replication system for patterned media applications, in concert with its jet-and-flash imprint lithography tech, enables mass-replication of master imprint templates with high fidelity at an orders-of-magnitude lower cost vs. fabricating the original master template.

Die-scale stress management to advanced annealing optimization

08/28/2009  Lithography overlay and leakage requirements are becoming increasingly stringent for the next-generation devices. Two case studies illustrate the role that stress non-uniformity has in misalignment and the effect of cumulative stress variations on device performance and leakage.

Double-patterning design challenges

08/20/2009  With the move towards fabless models and the use of double-patterning, it is critical that layout designers and manufacturing engineers remain engaged in the discussion of effective design rules that provide the types of yield, predictability and cost information that IC companies require.

IBM Advances DNA "Origami" Structures

08/19/2009  August 19 -- IBM researchers and collaborator Paul W.K. Rothemund, of the California Institute of Technology (CalTech), have made an advancement in combining lithographic patterning with self assembly

IBM: DNA "scaffolding" builds tiny circuit boards

08/17/2009  Researchers at IBM and the California Institute of Technology say they have come up with a solution to problems looming for future semiconductor manufacturing beyond the 22nm node: a combination of lithographic patterning and self-assembly that arranges DNA structures on surfaces compatible with current manufacturing equipment.

Nature Nanotechnology: DNA Shapes on Lithographically Patterned Surfaces Increase Semiconductor Density

08/17/2009  Scientists at IBM Research and the California Institute of Technology announced a method for structuring DNA shapes to help build miniaturized computer chips well beyond 22-nm processes. The research claims that chips will be more energy efficient and suited to mass production.

Using soluble gap-fill materials in VFTL integration

08/12/2009  Cu wiring based on dual damascene is beginning to hit fundamental limits of current via-first, trench-last (VFTL) integration, but thicknesses of films in the lithography stack for trench patterning can't scale as rapidly. This article outlines a novel approach for eliminating these variations using existing processes and equipment.

Developers push c-Si efficiency toward 20% with help from narrower interconnect

08/12/2009  Photovoltaic cells are getting steadily more efficient, and even the small area taken up by interconnect is shrinking to get more electrons flowing. Some of these developments were discussed at the recent Photovoltaic Specialists Conference in Philadelphia and at the accompanying PV America exhibition.

Extending double-patterning to 22nm

08/05/2009  Hamid Zarringhalam, EVP, technology, sales and marketing at Nikon Precision, talks about the need to extend double-patterning immersion lithography to 22nm. He also describes solutions to meet overlay accuracy requirements and a target throughput of 200wph.

Litho contaminants: Getting ready for EUV

08/05/2009  Jitze Stienstra, director, gas microcontamination, at Entegris, discusses the challenges of managing contaminants in leading-edge lithographic processes. When the industry begins using EUV lithography, the materials of construction of the tools, the process materials, wafers, reticles, and the photoresists, will all be potential sources of contamination.

MOSIS adding IBM's 180nm, 45nm SOI to foundry runs

07/31/2009  July 30, 2009: MOSIS, a prototyping and low-volume circuit production service, is expanding its shuttle runs to include two more of IBM's silicon-on-insulator (SOI) process technologies, for 0.18μm/200mm wafers and 45nm/300mm wafers.

Kalk: No litho option closed for 16nm

07/30/2009  Franklin Kalk, CTO at Toppan Photomasks, lists the lithography options for 22nm-16nm and below (immersion/double patterning, EUV, imprint) and why no option should be closed until a cost-effective solution is available with which everyone can live.

Mapper delivers e-beam tool for Leti joint work

07/21/2009  Continuing progress of the CEA-Leti-led three-year IMAGINE program to explore maskless lithography for the 22nm node and beyond, Mapper Lithography has delivered a "massively parallel" e-beam platform to Leti.

IMEC's Ludo Deferm: Behind the news

07/17/2009  IMEC's Ludo Deferm provides a look behind some major announcements the consortium made at SEMICON West: laser anneal over spike anneal, EUV mask cleaning, RuTa metallization showing promise for 22nm PVD.

Double patterning's 22nm win for breakfast

07/16/2009  Franklin Kalk of Toppan Photomasks reports for SST from Wednesday's Sokudo Lithography Breakfast, which offered a buffet of double patterning views as the transition from single-exposure 193i closes in at 40nm half-pitch.

SEMICON West: MEMS key to leading-edge semiconductors?

07/15/2009  July 15, 2009: A new technology being bundled into lithography equipment supporting leading-edge semiconductor manufacturing utilizes MEMS functionality to push current lithography technology as far as it can go.

ASML fulfills "holistic litho" plan with two tools, custom packages

07/15/2009  Citing the embodiment of its concept of "holistic lithography," ASML has unwrapped two hardware/software components to help chipmakers improve lithography process windows while avoiding costly and timely steps and maintenance downtime.

EUV: "Turned the corner to inevitability"

07/14/2009  SEMATECH's Bryan Rice gives a positive assessment of EUV and offers hope for getting companies to open their checkbooks for mask inspection infrastructure funding. It's no longer a matter of "if" but "when," he says -- and see news below of an imminent 100W source.

EV Group uncrates NIL stepper for micro-optics, nano R&D

07/13/2009  EV Group has unveiled a next-generation UV-nanoimprint lithography (NIL) step and repeat system eyeing use for microelectronics applications including optics/image sensors, lens arrays, and certain R&D nanoelectronics processes.




WEBCASTS



Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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