Lithography

LITHOGRAPHY ARTICLES



New Quick Polymer Stamp available for nanoimprint module

04/21/2009  April 21, 2009: NIL Technology now offers a Quick Polymer Stamp (QPS), facilitating a fast nanoimprint approach. The QPS is a working stamp, easily produced from a silicon or quartz master, to be directly used for UV nanoimprint lithography.

Micronic Laser Systems Moves to Acquire MYDATA

04/21/2009  Micronic Laser Systems AB intends to acquire MYDATA automation AB. In the proposed transaction, Micronic would acquire MYDATA from Skanditek Industriförvaltning and the minority shareholders against payment in the form of newly issued shares in Micronic. Combining Micronic and MYDATA will create large potential within the market for electronic packaging using Micronic's and MYDATA's complementary imaging and deposition technologies.

MIT makes 36nm lines with "interference" litho step

04/14/2009  A team of researchers at MIT have produced 36nm-wide lines using interference patterns and a photochromic material, and say the technique could be extended down to patterns on the scale of individual molecules.

Gartner: Few unscathed in worse-than-thought 2008

04/13/2009  A month ago Gartner pegged preliminary 2008 capex at a -25% slide to ~$33.46B. Turns out the firm was about $3B on the high side -- its "final" tally pegs 2008 semiconductor capex at just $30.7B, down -31.7% from 2007.

Micralyne, SVTC team up on 8-in. MEMS

03/30/2009  March 30, 2009: Micralyne Inc., a MEMS developer and manufacturer, and SVTC Technologies LLC, an independent MEMS and CMOS commercialization company, plan to collaborate on development and manufacturing of MEMS devices using 8-in. fabrication technology.

Heidelberg Instruments sells DWL 2000 to MESA+

03/26/2009  March 26, 2009: Heidelberg Instruments has announced the sale of an advanced DWL 2000 maskless laser lithography system to the MESA+ Institute for Nanotechnology at the University of Twente in The Netherlands.

Litho firms climb up heap in bloody 2008

03/18/2009  In a year that ultimately was terrible for the semiconductor industry, a few firms managed to claw their way up the list of sales leaders, though the top firms remain well entrenched, according to data from VLSI Research.

New Analytical Method Helps Control Hard-to-Measure Contamination

03/17/2009  March 17, 2009 -- CHASKA, MN -- Entegris, Inc. has introduced a new solution for accurately measuring and controlling volatile organic compounds that cause contamination in advanced semiconductor lithography processes.

SPIE observations: EUV vs. "all other" litho

03/10/2009  Ken Rygler offers his view of this year's SPIE event, and what's at stake in a proposed divergence of focus into EUV and "all other" litho technologies.

SPIE tracks the tightening litho horse race

03/09/2009  How much longer can the industry stay on an 'optics forever' path? EUV is gaining momentum and closing the gap, with most infrastructure in place (but one missing piece could be a "showstopper"). This year's SPIE's Advanced Lithography Conference in San Jose, CA, provided a detailed update on this tightening horse race.

Coopetition via radical collaboration

03/06/2009  Mark Slezak, director of lithography technology at JSR Micro, weighs in on Bernie Meyerson's (IBM) SPIE keynote urging industry "coopetition" -- a concept he notes is already alive and well in the materials sector.

NanoKTN, JEMI focus on atomic layer deposition

03/05/2009  March 4, 2009: The Nanotechnology Knowledge Transfer Network, based in the UK, and the Joint Equipment Materials Initiative are collaborating on focus-group event to examine the technique of atomic layer deposition.

Making a pitch for EUV

03/04/2009  Stefan Wurm, AMD assignee to SEMATECH and associate director of the lithography division, believes the industry wants to see EUV lithography work in anticipation of its potential at 22nm, 16nm, and possibly 11nm.

SPIE panel: DP is only litho solution for 22nm volume production

03/03/2009  Several lithography candidates seem promising for patterning circuits at 22nm and beyond: EUV, nano-imprint, direct write, and optical double patterning methods. But at an afternoon panel at SPIE hosted by Applied Materials, it became clear that only double patterning can deliver the necessary balance of performance and cost required for 22nm volume production.

Status report: 1X mask infrastructure

03/01/2009  Mark Melliar-Smith, CEO of Molecular Imprints, discusses the company's work to develop a 1X mask infrastructure.

Brion Technologies unveils SMO technology at SPIE

02/27/2009  Brion Technologies, a division of ASML, says its upgraded Tachyon source mask optimization (SMO) product targeted for the 22nm node, debuted at the SPIE Advanced Lithography Conference, enables full co-optimization of source and mask, witwh process windows improved by >40%.

IBM's Farrell: Computational litho, scaling to 16nm

02/25/2009  Tim Farrell, distinguished engineer at IBM's semiconductor R&D center, provides an update on efforts to implement comprehensive computational scaling computational scaling to 22nm, and discusses the possibilities at 16nm.

Does Tela-Blaze M&A spell end of DFM consolidation?

02/24/2009  Tela Innovations' announced acquisition of Blaze DFM essentially clears the industry playing field of startup DFM shops -- but that doesn't mean consolidation is entirely over.

Elionix expanding NanoTech System Center

01/16/2009  January 16, 2009: Elionix Inc., which supplies electron beam lithography systems, has begun construction to double its manufacturing output, scheduled to be completed in March.

Optimizing lithographic stack materials when using hyper-NA exposure tools

01/16/2009  As lithography pushes past 32nm resolution, the need to optimize stack materials, including resist, bottom anti-reflective coating (BARC), and substrate, has never been greater for IC manufacturers. This article describes a new simulation tool enabling engineers to more accurately model complex systems and make more informed decisions when selecting the best material solutions.




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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