05/02/2008  NIST says its work has helped resolve whether nanoimprint lithography (NIL) can accurately stamp delicate insulating structures on silicon wafers without damage -- and in fact makes them better. According to NIST, NIL "can produce superior nanoporous insulator layers in advanced semiconductor devices with significantly fewer -- and easier -- processing steps than conventional lithography."

04/30/2008  Apr. 30, 2008 - NIST says its work has helped resolve whether nanoimprint lithography (NIL) can accurately stamp delicate insulating structures without damage -- and in fact makes them better.

04/29/2008  MEMS/nano development tools supplier SUSS MicroTec has entered an agreement with Philips Research to create a new type of nanoimprint lithography (NIL) technology called Substrate Conformal Imprint Lithography (SCIL). The partnership aims to bring this feature to an existing equipment platform, and enable new approaches to large-area apps.

04/29/2008  Apr. 29, 2008 - Suss MicroTec and Philips Research say they are partnering to develop a new nanoimprint lithography technology targeting a niche in sub-50nm patterning between small rigid stamps and larger soft stamps.

04/29/2008  SUSS Microtec and Philips Research, Eindhoven, Netherlands, announced a license agreement to develop an enabling technology called substrate conformal imprint lithography (SCIL). The intention is to bring existing equipment platform with additional nanoimprinting (NIL) feature to the market, enabling new approaches to large-area imprint applications.

04/25/2008  Tohoku University has joined the network of Finland's Picosun Oy, developer of tools for the nanotechnology application of atomic layer deposition (ALD). "Our co-operation will lead to new results in implementation of ALD in nanotechnology applications and further strengthen the market position of our SUNALE ALD process tools in Japan," says Picosun. ALD, a gas phase chemical process, is used to create nano-scale thin coatings for various applications including MEMS and CMOS manufacturing.

04/25/2008  Apr. 25, 2008 - The European Commission's 7th Framework Program (FP7) is funding a new program on maskless lithography for IC manufacturing -- MAGIC -- to explore and promote maskless lithography technologies developed by a pair of European companies, including developing infrastructure on data preparation, proximity effect corrections, and processes.

04/23/2008  Apr. 23, 2008 - Taiwan's Macronix plans to push into NOR flash for handsets within the next three years, placing it in direct competition with Spansion and Numonyx, according to a local report.

04/23/2008  Apr. 23, 2008 - A pending memory recovery later this year and more migrations to smaller technology nodes will spur another round of immersion tool orders for ASML, according to an analysis from FBR Research.

04/23/2008  by Ed Korczynski, Senior Technical Editor, Solid State Technology
April 23, 2008 - Cleaning has always been essential for mask manufacturing, but today there is increasing concern to the point where fabs may soon clean masks in-house to prevent haze buildup. Meanwhile, EUV and NIL don't use pellicles, which almost certainly will mean cleaning masks in production. Seeking to address this need/opportunity is Applied Material, with its new Tetra Reticle Clean tool.

04/23/2008  NIL Technology has introduced a "high-accuracy but low-cost photonic stamp in silicon" to the company's product line geared to enable future photonic devices.

04/21/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
April 21, 2008 - KLA-Tencor's Wafer Plane Inspection software attempts to do with computation what Zeiss' AIMS and Applied Materials' Aera2 try to do with optics: sort printable defects from harmless anomalies and false defects (backed up in a paper coauthored with Intel). Success will facilitate meaningful inspection of complicated OPC masks, and more creative solutions to advanced imaging problems employed in production.

04/16/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
April 16, 2008 - With aerial images now having simpler geometry than OPC mask designs, it may be time for aerial image inspection to replace microscopic mask measurement. If it performs as advertised, Applied Materials' reentrance into the mask inspection tool market, the Aera2, could enable more aggressive RET strategies, lower reticle costs, and help make chip yield more predictable at 45nm and 32nm.

04/08/2008  by Brian Dance, European Contributing Editor, Solid State Technology
Ian Burnett, past chairman of JEMI UK, tells WaferNEWS European correspondent Brian Dance what was successful about the just-completed MEDEA+ R&D programs, and how the new programs dubbed CATRENE will force the R&D community to relate expenditures to tangible benefits for society -- and "become the blueprint for government supported R&D not only throughout Europe but at a global level."

04/08/2008  by Tom Cheyney, Senior Contributing Editor, Small Times
Electron-beam direct write, nanoimprint lithography (NIL), and other potentially disruptive semiconductor nanopatterning technologies drew strong attendance and elicited spirited discussion during the SPIE Advanced Lithography conference, as Small Times' Tom Cheyney reports.

04/03/2008  by Debra Vogler, Senior Technical Editor, Solid State Technology
April 3, 2008 - JSR Microelectronics tells WaferNEWS about its new "freezing material" targeting brightfield applications (i.e., line first double-patterning (DP) processes), and why logic and some memory applications should be a good fit.

04/01/2008  Two recent announcements regarding semiconductor photomasks are good news for the industry, with one being a contamination-related breakthrough.

03/28/2008  by Bob Haavind, Editorial Director, Solid State Technology
A presentation by RIT engineers at this year's SPIE Advanced Lithography conference suggested the intriguing possibility of utilizing contrast differences for the TE/TM modes of exposure light to enable double patterning with frequency doubling imaging -- a technique that might provide a single-exposure alternative to double exposure/double patterning schemes at sub-45nm nodes.

03/25/2008  by Bob Haavind, Editorial Director, Solid State Technology
Problems with complex circuit patterns using alternating phase shift masks for low k₁ lithography led Intel to experiment with using trillions of pixels for imaging. A number of papers at this year's SPIE Advanced Lithography Conference described the techniques developed to successfully do the critical first metallization layer (M1) on a microprocessor using pixelated phase-shift masks.

03/24/2008  by Katherine Derbyshire, Contributing Editor, Solid State Technology
Traditionally, achieving high resolution with negative imaging has been difficult. Research presented by Fujifilm Electronic Materials at this year's SPIE Advanced Lithography conference showed how to tune the resist imaging threshold to clear "dark" and "bright" regions, and ultimately double the pitch frequency and thus the density of lines and spaces.