07/17/2007  What happens when you put a design software vendor, a chip manufacturer, and a photomask maker all at one table and ask them to talk about yield? Not surprisingly, the software vendor finds himself on the hot seat.

07/16/2007  July 16, 2007 - At SEMICON West, European R&D consortium IMEC is disclosing it results after a year of 32nm half-pitch work, noting progress in all three of its areas of focus: high-index 193nm immersion litho, double-patterning, and EUV.

07/16/2007  A quick roundup of news and views ahead of SEMICON West finds ASML tipping a KrF version of its Twinscan and announcing a first customer for its "ultimate" XT:1900i immersion tool; Cymer's "socialized medicine" for laser light sources; and Synopsys weaving its tools together to drive next-generation yields.

07/16/2007  On the surface, the latest DFM-industry consolidation appears to be a win-win for both Cadence Design Systems Inc. and Invarium Inc., though interviews with WaferNEWS suggest much work still has to be done to figure out the exact combination and roadmap going forward.

07/12/2007  July 12, 2007 - In the latest sign of consolidation in the DFM universe, Cadence Design Systems Inc. has acquired Invarium Inc., a developer of lithography modeling and pattern-synthesis technology, creating what the firms say is combined DFM solution that can enable, prevent, detect, correct, and optimizate manufacturing effects on advanced geometry designs.

07/11/2007  July 11, 2007 - Nikon Precision Inc. has released two new DUV lithography scanners, built on its Tandem Stage platform, to improve productivity and enhance overlay performance.

07/10/2007  Despite the fact that it's done much of its manufacturing in nanoscale dimensions for years, the semiconductor industry hasn't yet had much use for the unique nanoscale properties of the nanoparticles, nanowires, quantum dots, etc. usually considered nanotechnology, nor found much use for the nanoscale patterning processes developed by the chipmakers. But that may be starting to change, judging by the crop of emerging technologies selected for SEMICON West's Technology Innovation Showcase.

07/10/2007  As the industry marches from 90nm to 65nm and 45nm, it has become increasingly difficult to achieve fast yield ramp due to random defects, process variations, and other design-for-manufacturing (DFM) issues localized in layout hot spots. Hoping to become the leading company bridging the gap between IC design and manufacturing is Takumi Technology with its automatic layout repair/optimization software.

07/06/2007  EXECUTIVE OVERVIEW This month's edition of Chip Forensics by analyst Dick James delves into Flash technology, including the Samsung K9F2G08U0M 2-Gb single-level cell (SLC) Flash.

07/01/2007  IBM recently announced the first application of a breakthrough self-assembling nanotechnology to conventional chip manufacturing, borrowing a process from nature to build the next-generation computer chips.

07/01/2007  In response to consumer demand for smaller, faster, and more capable electronics, semiconductor process designers and chip fabricators have adopted optical lithography processes to increase chip capacity by decreasing circuit linewidths.

07/01/2007  Newly robust electroforming processes enable rugged, affordable microsystems

06/26/2007  Intel typically uses its annual "Research Day" to provide a glimpse into potential commercial applications for the chipmaker's technologies. But this year's event (June 20) also demonstrated the way Intel's technology advances the chipmaker's own electronics manufacturing -- showing how "computational lithography" will be the backbone of Intel's proprietary DFM strategy for the foreseeable future.

06/22/2007  Fraunhofer Center Nanoelectronic Technologies uses Vistec tool for nano chip innovations

06/21/2007  June 21, 2007 - A new study by Wright Williams & Kelly Inc. and Strategic Marketing Associates sheds light on what people in the industry think will be most likely to hit production process lines in the next 2-5 years, and which ones may take longer than expected to be adopted into manufacturing lines, if ever.

06/19/2007  June 19, 2007 - Matsushita Electric Industrial Co. says it has begun the "world['s] first" mass production of 45nm LSI chips at its factory in Uozu, central Japan, using ArF immersion lithography (NA>1) with "proprietary super-resolution enhancement technology" and multilayer wiring using low-k dielectrics.

06/14/2007  June 14, 2007 - Silterra Malaysia says it has signed a "joint development project" with European R&D consortium IMEC to create a foundry-compatible 90nm CMOS process technology, based on IMEC's process, with intention to scale to 65nm (while developing a 110nm derivative in parallel). The two already had worked on 0.13-micron process technology under a deal signed in June 2004.

06/14/2007  June 14, 2007 - Luminescent Technologies Inc. says it has raised $9 million in a new round of financing, led by new investor Adams Capital Management along with existing investor Sevin Rosen Funds. The funds will be used to continue driving adoption of the company's inverse lithography technology (ILT), which it is touting as an alternative to optical proximity correction (OPC), offering better pattern fidelity and broader lithography process windows.

06/14/2007  June 13, 2007 - Providing updates on work performed with its 32nm CMOS research partners at this week's VLSI Symposium, IMEC says it has improved its process to yield "reproducible" finFETs with fin widths down to 5nm, and high aspect ratios, using 193nm immersion lithography and dry etching. However, "several bottlenecks have to be overcome" before the finFETs can be viable in manufacturing.

06/14/2007  June 13, 2007 - STMicroelectronics says it has taped out the design for a low-power system-on-chip (SoC) "demonstrator" device with a multiple threshold transistors, dual-core CPU and associated memory hierarchy. The process improves speed by 20% vs. 65nm designs or reduces leakage current by half when in operation (and by "several orders of magnitude" when in retention mode), and takes up half the silicon area.