Packaging

PACKAGING ARTICLES


Mentor Graphics and TSMC collaborate on 20nm IC physical verifications

05/29/2013 

Mentor Graphics Corp. today announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations.
Signetics announces plans to increase their flip chip package assembly capacity

05/28/2013 

Signetics Corporation today announced that it has again approved capex plans that will further expand their capacity for flip chip package assembly at their factory in Paju, South Korea.
New power management IC helps reduce thermal stress on processors in phones and tablets

05/28/2013 

ams AG, a provider of high performance analog ICs and sensors, today introduced the AS3721, a power management IC (PMIC) with an innovative remote-feedback circuit that helps reduce the thermal stress of applications processors in smartphones and tablets.
Invensas demos new high bandwidth packaging solution for mobile devices at 2013 ECTC

05/22/2013 

Invensas Corporation, a subsidiary of Tessera Technologies, Inc., will showcase its latest mobility solution, an ultra-high bandwidth Bond Via Array (BVATM) Package-on-Package (PoP) product, at the upcoming IEEE Electronic Components & Technology Conference (ECTC) in Las Vegas, NV on May 28 - 31, 2013.
North American semiconductor equipment industry posts April 2013 book-to-bill ratio of 1.08

05/22/2013 

North America-based manufacturers of semiconductor equipment posted $1.17 billion in orders worldwide in April 2013 (three-month average basis) and a book-to-bill ratio of 1.08.
Mentor and Tezzaron optimize Calibre 3DSTACK for 2.5/3D-ICs

05/20/2013 

Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings.
What is interconnect and why is it so important?

05/20/2013 

Cobalt and Silicon Nitride Barrier Cap Films for Copper Low k Interconnects

05/20/2013 

Process Integration of 3D Capacitors into 22nm Interconnect Stacks

05/20/2013 

Mean Free Path for Vertical Carbon Nanotube Interconnects Approaches Copper

05/20/2013 

Graphene Experimentally Demonstrated to have Lower Resistivity than Copper

05/20/2013 

Experimental Demonstration of Monolithic 3D-IC Technology

05/20/2013 

Near-Zero Keep-Out Zone for Through Silicon Via Technology

05/20/2013 

SEMI's 3DIC standards activities

05/18/2013  I have said many times that it will be impossible for a complicated technology like 3DIC to ever become commercial without standardization.
Wafer-level packaging of ICs for mobile systems of the future

05/18/2013  The most functionality at the least cost is the promise of wafer-level packaging (WLP) when dealing with complex integrated circuits (IC) with a high number of input/output connections to the outside world.
Yole Developpement conducts 2.5D, 3DIC and TSV interconnect patent investigation

05/15/2013 

Yole Développement announced its 2.5D, 3DIC and TSV Interconnect Patent Investigation report. For this analysis of 3D packaging technology patents, more than 1800 patent families have been screened.
Global semiconductor sales outpace last year through Q1 of 2013

05/14/2013 

Sales in March 2013 were up slightly compared to February 2013 and March 2012.
Silex joins ENIAC project to develop new solutions for TSV and wafer bonding

05/13/2013 

Silex Microsystems, the world’s largest pure-play MEMS foundry, today announced that it has joined an international European Union-funded program aimed at developing a new MEMS manufacturing platform based on advanced inkjet-based printing technologies.
MOSIS collaborates with imec, Tyndall and ePIXfab on silicon photonics

05/02/2013 

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with imec, Ireland's Tyndall National Institute and ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.

EI

05/02/2013 

Endicott Interconnect Technologies, Inc. (EI) announced that its System-In-Package (SiP) technology performed successfully in a military test of a small hit-to-kill interceptor designed to defeat rocket, artillery and mortar attacks.  



WEBCASTS


Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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