Semiconductors

SEMICONDUCTORS ARTICLES



SEMATECH outlines maskless issues, proposes consortium

05/17/2010 

Among key takeaways from SEMATECH's Litho Forum last week in NYC was a proposal to create a consortium to support multibeam mask writing efforts, similar to what's being done for EUV.

NOR flash revenue set to grow in 2010 after downturn

05/14/2010 

Buoyed by improved demand and a brightening macroeconomic environment, NOR flash memory market revenue is projected to return to growth in 2010, according to iSuppli Corp. The climb will be modest: from $4.6 billion in 2009 to $4.8 billion in 2010.

Sonoscan demos MEMS cavity seal integrity inspection

05/13/2010 

Defects most frequently take the form of voids within the MEMS cavity seal. In some locations on a wafer, the seal may be breached.

Leveraging nanoimprint lithography for diverse applications

05/12/2010 

Molecular Imprints founder/CTO S.V. Sreenivasan shared the company's J-FIL nanoimprint lithography approach with attendees at a recent IEEE San Francisco Bay Area Nanotechnology Council meeting, reports Neha K. Choksi.

TSMC approves $1.6B for new fabs, upgrades

05/11/2010 

Chip foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) has greenlighted investments in fab infrastructure, including a new 300mm gigafab -- but there may not be any immediate capex adjustment for it, and that may be a good thing.

Asys plucks DynTest for LED singulation tech

05/10/2010 

The Asys Group say it has acquired the IP and patents of fellow German firm DynTest Technologies, seeking to apply the company's wafer singulation technology to high-brightness LEDs.

Novellus tips WN film for ≤3X memory Cu interconnects

05/10/2010 

Novellus says it has devised a new process technology for connecting tungsten vias to Cu interconnects in 3X node and below memory devices.

Combinatorial tooling for cost-effective, efficient ALD

05/06/2010 

Researchers from Intermolecular describe an atomic-layer deposition (ALD) process development chamber that allows multiple site-isolated depositions on different quadrants of a 300mm wafer, with data from a case study of ZrO2 film development.

Analyst: DRAM "lurched" to profits in 2009; DDR3 changeover imminent

05/05/2010 

The year 2009 started at one extreme (bad), but by year's end the DRAM sector had managed to "lurch" to the high end of the scale to finish the year with its first profitability since 2007, according to data from iSuppli.

Improving 22nm design space with source/design optimization

05/04/2010 

Execs from Texas Instruments and Luminescent Technologies describe a "source/design optimization" technique that blends source/mask optimization (SMO) techniques with design rules, and realizes significant improvements in overall die area.

EUV players hit 100W output with LPP source

04/27/2010 

The Extreme Ultraviolet Lithography System Development Association (EUVA) says it has surpassed 100W output at intermediate focus for an EUV light source, another big step to address a big hurdle facing EUV lithography as a production-viable candidate for next-generation semiconductor manufacturing.

IBM: 3D nanopatterning goes sub-15nm, beats e-beam litho

04/27/2010 

A new nanopatterning technique demonstrated by IBM can achieve 15nm resolutions, and could supplant e-beam lithography in applications ranging from CMOS to self-assembled nanoscale objects, and for materials including "molecular glass."

Fairchild, Infineon compatibility agreement aligns power MOSFET packages

04/22/2010 

Fairchild Semiconductor and Infineon Technologies formed a packaging partnership for their power MOSFETs in the MLP 3x3 (Power33 or S3O8) and PowerStage 3x3 packages.

MHI ships first 200mm MEMS bonder

04/21/2010 

Mitsubishi Heavy Industries says it has delivered its first automated room-temperature bonding system for 200mm wafers for production use, to a MEMS manufacturer in Japan.

MRS Day 4: TSVs and CMOS+MEMS, wafer bonding, CNT interfaces, ALD for rare-earth HK, graphene redux

04/19/2010 

Highlights from Day 4 of the 2010 MRS Spring meeting, reported by Techcet's Michael A. Fury: TSVs and flexible interconnects for 3D CMOS/MEMS; 300mm BCB wafer bonding; carbon nanotube interfaces for interconnects and vias; phase-change memory devices; interfaces during ALD of rare earth-based high-k dielectrics; and graphene's use in on-chip interconnects and transparent conductor electrodes.

MRS Day 2: CVD for Cu, low-k etch stop, future FETs, graphene "atom hopping"

04/14/2010 

Techcet's Michael A. Fury continues his series of observations from this year's MRS Spring meeting in San Francisco. From Day 2: CVD for Cu interconnects, controlling low-k etch-stop layers, materials challenges for future FETs, "atom hopping" in graphene, and oxide nanoelectronics on demand.

MRS Spring 2010 meeting, Day 1: Charge-trapping NVM, organics, graphene, PV

04/13/2010 

In an SST exclusive, Techcet's Michael A. Fury offers a series of observations from this year's MRS Spring meeting in San Francisco. First up: Day 1 discussions ranging from memory architectures, organic electronics, graphene, and solar photovoltaics.

EU group takes stride toward optical interconnects

04/12/2010 

An EU-funded project has come one step closer to its goal of building silicon photonics circuits, with the creation of a fully CMOS-compatible laser source coupled to a silicon waveguide.

Singapore launches MEMS consortium

04/09/2010 

A group of eight global companies, supported by local research and government, have formed a consortium to facilitate and grow Singapore's expertise in microelectromechanical systems (MEMS).

Toshiba's 25nm trial ups ante for NAND scaling, next-gen litho

04/06/2010 

Toshiba reportedly is prepping a ¥15B (US $157M) investment in a <25nm NAND flash test line, eyeing mass production in 2012, a move that not only tightens the NAND flash scaling wars, but also could narrow the insertion point for a next-generation lithography set.




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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