08/05/2009  Jitze Stienstra, director, gas microcontamination, at Entegris, discusses the challenges of managing contaminants in leading-edge lithographic processes. When the industry begins using EUV lithography, the materials of construction of the tools, the process materials, wafers, reticles, and the photoresists, will all be potential sources of contamination.

08/05/2009  The BrightSpots 3D IC Forum came to a close on Friday, July 24. Out of 3 topic areas covering technology progress, supply chain issues, and standards development, the discussions around technology progress were clearly the most active, both from a panelist and attendee perspective. What follows is a summary of each discussion. Where topics overlapped, and discussions were brief, the summaries have been combined into one.

08/05/2009  Larry Smith, sr. member of the technical staff in SEMATECH's 3D interconnect division, discusses toolset acquisitions at the U. of Albany's CNSE, where work focuses on replacing traditional global interconnect and intermediate level processes.

08/05/2009  Building on its Galaxy imaging platform, DEK has used the foundation of the technology's supreme accuracy and precision to develop a system specifically for processing thinned silicon wafers.

08/05/2009  Steven Dwyer, VP & GM, North America at EV Group, provides highlights of 3D integration papers the company presented at SEMICON West. By achieving alignment accuracy down to 200nm, thin wafer handling at thicknesses <10μm, and 300mm-capable wafer bonding, he says the company is ready for whatever comes along.

08/04/2009  André Rouzaud, VP deputy, division heterogeneous integration at Leti, describes two generic integration schemes at the wafer level: one for integrating chips from different sources without design access, another for those with design access. He also addresses thin wafer handling.

08/03/2009  FEI exec Joseph Race shows how the company's Tecnai Osiris scanning/transmission electron microscope (S/TEM) addresses an emerging need amid device-size shrink and proliferation of new semiconductor materials: a tool that combines the ease-of-use of EDX analytics with an elemental mapping speed comparable to STEM imaging.

07/31/2009  July 30, 2009: MOSIS, a prototyping and low-volume circuit production service, is expanding its shuttle runs to include two more of IBM's silicon-on-insulator (SOI) process technologies, for 0.18μm/200mm wafers and 45nm/300mm wafers.

07/30/2009  Franklin Kalk, CTO at Toppan Photomasks, lists the lithography options for 22nm-16nm and below (immersion/double patterning, EUV, imprint) and why no option should be closed until a cost-effective solution is available with which everyone can live.

07/28/2009  Hans Stork, Group VP & CTO at Applied Materials discusses the progress being made in developing cost-effective 3D/TSV solutions. In particular, the company is working in an open architecture environment to ensure complete solutions are ready for end users.

07/28/2009  Foundries have been growing at a better rate than the semiconductor industry for several years, but the global economic quagmire compounds a fundamental restructuring of the pure-play contract chipmaking sector centered on how to deal with facilities being made obsolete in the changing marketplace, according to a new report from iSuppli.

07/28/2009  Inventories are spiking in the solar supply chain due to oversupply coupled with lackluster demand, and the glut will cause price erosion from raw materials to cells, according to a report from iSuppli.

07/27/2009  ATMI exec Tod Higinbotham describes his company's latest "green" product, unveiled at SEMICON West: the RegenSi 74, an improvement to its advanced test wafer recycle and reclaim products that it claims can cut film removal cycle times in half and greatly reduce the amount of chemicals required for wafer reclamation.

07/27/2009  Horacio Mendez, executive director of the SOI Industry Consortium, gave SST previews a new study that compares the manufacturability, performance, and cost of 3D transistors using silicon-on-insulator (SOI) vs. bulk. He also discusses the group's new "Simply Green" initiative to help emphasize SOI's power benefits vs. bulk Si.

07/22/2009  July 21, 2009: Representatives CEA-Leti, STMicroelectronics, IBM, and officials from across France have gathered to officially launch the Nano2012 R&D program, a public/private program led by ST to create advanced R&D clusters to develop new semiconductor technologies.

07/21/2009  Continuing progress of the CEA-Leti-led three-year IMAGINE program to explore maskless lithography for the 22nm node and beyond, Mapper Lithography has delivered a "massively parallel" e-beam platform to Leti.

07/21/2009  July 20, 2009: FEI Corp. has unveiled a new scanning/transmission electron microscope (S/TEM) that it says "dramatically increases productivity" for analysis work in applications such as semiconductor manufacturing and materials analysis.

07/17/2009  At SEMICON West, SAFC Hitech unveiled details of its six-year-out (through 2014) materials roadmap for metalorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) processes on silicon semiconductor substrates, outlining development paths for advanced memory and logic including barrier layers, interconnects, dielectrics and metals.

07/17/2009  EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).

07/17/2009  EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).