03/01/2009  Conference preview and exhibitor showcase.

02/27/2009  Brion Technologies, a division of ASML, says its upgraded Tachyon source mask optimization (SMO) product targeted for the 22nm node, debuted at the SPIE Advanced Lithography Conference, enables full co-optimization of source and mask, witwh process windows improved by >40%.

02/27/2009  February 27, 2009: Researchers at Northeastern University created a network of nanowires that can be scaled up more efficiently and cost-effectively to create bigger displays -- such as the Nasdaq sign in New York City's Times Square.

02/25/2009  Tim Farrell, distinguished engineer at IBM's semiconductor R&D center, provides an update on efforts to implement comprehensive computational scaling computational scaling to 22nm, and discusses the possibilities at 16nm.

02/24/2009  Tela Innovations' announced acquisition of Blaze DFM essentially clears the industry playing field of startup DFM shops -- but that doesn't mean consolidation is entirely over.

02/24/2009  Everyone expects the industry climate to get worse before it gets better. But perhaps how bad and how quickly is catching some by surprise. By several metrics, SEMI's latest monthly summary of tool demand is as bad as seen in two decades -- and even longer.

02/24/2009  Applied Materials, Inc. has joined the international EMC-3D semiconductor equipment and materials consortium, which focuses on 3D chip stacking and MEMS integration.

02/23/2009  L

02/19/2009  By Gail Flower, Editor-at-Large This article provides a broad review of the issues affecting socket usage: lead-free challenges, finer pitch adjustments, cost control, standardization, practical customer concerns, and improvements needed for 3D packages and other innovations on the horizon. Through conversations with industry experts, we explore a few common themes from this year's Burn-in and Test Socket Workshop (March 8 -11, 2009) in Mesa, AZ.

02/19/2009  By Fred Taber, General Chairman, BiTS For the most part, the universe of wafer probes and the one for sockets have customarily been separate and distinct. Yet they parallel each other in so many ways: they provide temporary electrical contact to a device under test, and have many common technical challenges, such as contact resistance, signal integrity, tight pitch and cleaning, among many others.

02/18/2009  University research consortium Semiconductor Research Corp. has brought onboard European nanoelectronics R&D consortium IMEC to join work in creating "environmentally friendly" processes and materials for advanced semiconductor manufacturing.

02/18/2009  Worldwide silicon wafer area shipments and revenues fell in 2008 for the first time since 2001 as everything fell apart in the final months of the year, according to date from SEMI's Silicon Manufacturers Group (SMG).

02/17/2009  The j360 Silicon PathFinder 3D Platform from Javelin Design Automations supports 3D stacked IC design using through silicon vias (TSV). The design tool reportedly extends the Javelin PathFinding methodology and j360 Silicon PathFinder platform to support virtual chip design for co-optimization of system design and 3D interconnect-packaging technologies

02/16/2009  In a bid to expand applications for 3D packaging, NEC has developed a 3D chip-stacked flexible memory to support large-scale high-performance systems-on-chip (SoC).

02/16/2009  By Bernie Siegal, Thermal Engineering Associates, Inc.
A thermal test chip is usually designed to help thermal engineers answer critical thermal packaging or material questions. These chips either target general purpose applications, or thermal simulation of a very specific application chip. General-purpose chips must meet some key requirements. This article outlines these requirements, and describes a chip that meets them in the simplest manner possible.

02/05/2009  SEMI has released a "guidance document" for a photovoltaic standards roadmap that lists dozens of standards and guidelines it says are applicable to PV manufacturing to save costs and spark innovation.

02/03/2009 

International SEMATECH Manufacturing Initiative (ISMI), the global consortium of major semiconductor manufacturers, today announced the launch of its new Environment, Safety & Health (ESH) Technology Center in Austin, Texas. The Center will be dedicated to providing green technology solutions that lead to reduced energy consumption, lower costs, and greater productivity in semiconductor manufacturing.

02/03/2009 

International SEMATECH Manufacturing Initiative (ISMI) has launched a new Environment, Safety & Health (ESH) Technology Center in Austin, Texas, dedicated to providing green technology solutions that lead to reduced energy consumption, lower costs, and greater productivity in semiconductor manufacturing.

01/30/2009  In photochemical purification applications, bubble elimination is as important as particle removal. This paper describes a technique developed to rapidly eliminate microbubbles -- which affect yield -- during filter startup in a two-stage dispense system. Experimental results suggest that providing a constant pressure to the fluid after wetting the filter makes it possible to effectively eliminate microbubbles in the fluid.

01/28/2009  An extended partnership between SVTC and Entrepix widens their outsourced CMP services to 300mm wafers, for both semiconductor manufacturers and suppliers -- and, execs tell SST, gets them on an early track for growth areas several years down the road.