Semiconductors

SEMICONDUCTORS ARTICLES



March Events Preview

03/03/2008  ; March is a busy travel month for the Advanced Packaging editors. In the next few weeks, we'll be reporting from Arizona, where both the BITS Workshop (March 9–12, 2008) and IMAPS' International Device Packaging Symposium, in conjunction with the Global Business Council (March 17–20, 2008), will be taking place; as well as Shanghai, where Gail Flower, editor-in-chief, will attend SEMICON China (March 18–20, 2008).

SST On the Scene: SEMATECH's progress in immersion, EUV

03/03/2008  March 3, 2008 -- Stefan Wurm, program manager, EUV strategy at SEMATECH, updates Solid State Technology's Senior Technical Editor Debra Vogler on that group's progress in immersion lithography and EUV. Highlighted is progress on EUV mask defectivity and the first integrated chip with a layer made using EUV lithography. He also discusses the nanocomposite approach to high-index immersion lithography and the consortium's efforts to monitor non-optical lithography methods (e.g., NIL).

Snowstorms and Sockets

03/01/2008  Driving around after a recent snowstorm in the Northeast U.S., and seeing how rapidly the roads are kept clear, got me thinking about socket contact cleaning.

Zarlink: Take our analog fab, please!

02/29/2008  Feb. 29, 2008 - In what is essentially the last in a divestiture of its semiconductor foundry operations, Zarlink Semiconductor has sold its analog foundry in Swindon, UK to a subsidiary of domestic electronics component supplier MHS Electronics -- with a grand pricetag of €1 (~$1.51).

Zygo buys Solvision for backend inspection play

02/29/2008  Feb. 29, 2008 - Zygo says it has acquired the assets of Solvision, a Canadian provider of visual inspection equipment, for an undisclosed amount.

SST On the Scene: Lars Liebmann on DFM, scaling

02/29/2008  Feb, 29, 2008 - In this exclusive video interview, IBM's Lars Liebmann talks about his papers presented at this week's SPIE, including persistent misconceptions about restricted design rules, and the need for designers to react to systematic and stable effects with broad, coarse layout adjustments vs. minor movements based on a specific moment. He also discusses the opportunities at 22nm with "soft" and "hard" DFM, and how these concepts will be required to keep the scaling path profitable.

ASMI to stakeholder: No board changes

02/28/2008  Feb. 28, 2008 - In what is becoming a common sight on public newswires, another chip industry company is airing out some dirty laundry with an unusually public statement about internal affairs -- this time ASMI's rejection of a stakeholder's calls for replacing its board members.

SEMATECH to begin nanoimprint lithography work with Molecular Imprints' new Imprio 300

02/28/2008  SEMATECH, an association of semiconductor technology developers, has purchased Molecular Imprints' new Imprio nanoimprint lithography (NIL) tool, announced this week. SEMATECH will use the Imprio 300 to demonstrate the feasibility of for semiconductor production at 32nm and below.

SPIE: Tela Innovations lays it all out straight

02/28/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
At about the 90nm node, circuit features so much smaller than the exposure wavelength led to increased circuit variability, lithography hotspots, and limited yields (and applying restrictive design rules had limited success). Now, startup Tela Innovations is proposing a radical step to solve the industry's layout problems: employing pre-defined linear topologies, workable with 32nm and double-patterning and down to 22nm.

Rohm & Haas, IBM eye Cu CMP for 32nm-22nm

02/27/2008  Feb. 27, 2008 - Rohm & Haas Electronic Materials/CMP Technologies and IBM are adding to their collaborative plate, with a pact to develop CMP processes for integrating copper and low-k dielectrics, in order to create copper CMP consumables for 32nm and 22nm device manufacturing.

Tela funding tops $5M, includes Intel's VC arm

02/27/2008  Feb. 27, 2008 - Startup Tela Innovations says it has raked in about $5M in funding over two rounds since mid-2006, including an infusion from Intel's VC arm.

IBM, ASML, others gain SPIE Fellow honors

02/27/2008  Feb. 27, 2008 - Eight new Fellows have been added to SPIE's roster to honor their scientific and technical contributions in optics/photonics/imaging, and to the group in particular. Also, receiving awards at this year's SPIE Advanced Lithography symposium were researchers from ASML, IBM, KLA-Tencor, and the U. of Wisconsin/Madison.

SPIE: SEMATECH starting imprint litho work, buys MII tool

02/27/2008  Feb. 27, 2008 - SEMATECH has purchased Molecular Imprints new Imprio 300 tool to demonstrate the feasibility of nanoimprint lithography for 32nm and below semiconductor production. Initial work will focus on demonstrating and enhancing overlay performance, and identify development areas to accelerate the introduction of the technology into manufacturing. Delivery is scheduled for mid-2008.

SPIE: Philips, XTREME push EUV source to 500W

02/27/2008  Feb. 27, 2008 - Presenting at the SPIE Advanced Lithography Symposium, Philips Extreme UV and XTREME Technologies offered proof-of-principle experiment results showing their gas-discharge plasma source can be scaled to 100kHz operation frequency, which translates to a record 500W EUV source power -- more than enough to meet requirements for high-volume semiconductor manufacturing.

SPIE: AMD, IBM tip first "full field" EUV chip

02/27/2008  by Bob Haavind, Editorial Director, and James Montgomery, News Editor, Solid State Technology
Feb. 27, 2008 - AMD and IBM say they have produced a working 22mm x 33mm test chip built with 45nm process technologies using EUV lithography for the first critical layer of metal interconnects, pushing beyond previous EUV efforts that involved "narrow field" portions of the design.

Equipment supplier Rudolph joins chipmakers in Sematech nanoelectronics program

02/26/2008  Rudolph Technologies Inc. has become the first semiconductor equipment supplier company to join Sematech's Metrology Program headquartered at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany in New York.

Double patterning will challenge litho, metrology, push feedback, computation

02/26/2008  by Bob Haavind, Editorial Director, Solid State Technology
Feb. 26, 2008 - Plenary talks at this week's SPIE Advanced Lithography Conference reviewed the road ahead for lithography, from how far 193nm immersion can be pushed (probably 32nm, helped double patterning, new lens materials/fluids, and 3D) to the projected readiness of an EUV infrastructure (maybe by 2010-2012), and the progress and stalls in ongoing work to achieve success in both areas.

Bede: Buyout offer on, then off the table

02/26/2008  Feb. 26, 2008 - In the span of a week, UK-based Bede, a provider of X-ray metrology tools, said that it had finally received an offer from a suitor after being first approached last summer, but that the offer was below current market value, and now the deal's off.

ANALYSIS: KLAC-ICOS makes sense, pending typical M&A quirks

02/26/2008  by James Montgomery, News Editor, Solid State Technology
Feb. 26, 2008 - The proposed combination of KLA-Tencor and ICOS Vision Systems makes sense for both sides, both financially and in market positioning, though as always some questions need to be answered about just how smooth any such M&A will be.

How TI plans to go from 'fab lite' to 'fab-lite-r', while boosting analog

02/26/2008  by Bob Haavind, Editorial Director, Solid State Technology
Feb. 26, 2008 - Texas Instruments' external development/manufacturing VP Thomas Thorpe gave an enlightening address about the ongoing benefits derived from the company's 'fab-lite' strategy at the recent Strategic Materials Conference in Half Moon Bay, CA. No more advanced CMOS wafers and 32nm work is going on inside TI's own fabs -- but he left door open that they might return in the future.




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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