3D progress seen at SiP global summit

11/01/2011







The SiP global summit was held during 2011 Semicon Taiwan in Taipei. It consisted of the 3D IC Test Forum "Test Challenges and Solution in the New Era of Heterogeneous Integration," chaired by Mike Liang, President and CEO, KYEC; the 3D IC Technology Forum, "Embracing the Era of 2.5D & 3D ICs," chaired by Dr. Ho-Ming Tong, GM and chief R&D officer, ASE Group; and the Embedded Substrate Forum, "Bridging the Last Mile of Heterogeneous Integration," chaired by Dr. Kuo-Ning Chiang, Professor, director, Advanced Packaging Research Center, NTHU.

Dr. Phil Garrou, blogger and analyst

Chairman Tong stood by the prediction he made at last year's meeting that serious commercialization of 2.5D and 3D ICs would likely begin in 2013.

Takayuki Watanabe, VP of Elpida's TSV packaging development group, gave a detailed presentation titled "TSV Technology for 3D DRAM." He described TSV production flow in Elpida where DRAM production and thinning is done in Hiroshima and stacking and assembly in Akita-Elpida.

In July Elpida announced sampling of their 8Gb DDR3 SDRAM. The device is a "low power 8Gb DDR3 SDRAM that consists of four 2Gb DDR3 SDRAMs fitted to a single interface chip using TSV." Elpida believes that the new devices in notebook PCs will demonstrate a 20% reduction in operating power and a 50% reduction in standby power compared with systems that use the standard SO-DIMM configuration. Power consumption is reduced because the TSVs shorten the interconnects between the chips, thus reducing parasitic resistance and capacitance. In addition, chip height is decreased and the DIMM socket is eliminated. Chip mounting area is reportedly reduced 70%. A 16Gb module (consisting of two 4 chip stacks) occupies far less room (11mm ?? 15mm) than its SODIMM equivalent (67mm ?? 30mm).

Wide IO memory technology appears to be the future for mobile products mainly because it brings lower power consumption in a smaller, thinner package while being scalable for future bandwidth requirements. JEDEC is currently working to develop standards for such wide IO memory products.

About a year ago Elpida Memory, Powertech Technology (PTI), and United Microelectronics Corporation (UMC), announced a 3-way 3D IC partnership to Elpida had previously announced their partnership with Powertech Technology Inc. and UMC to build 3D chips for the mobile, high-end graphics and computer markets.

In the 3D IC Test Forum, it was clear that multiple packaging and testing challenges must be met to meet the production yields required to take 3D from concept to commercialization. It is crucial that the entire supply chain of material suppliers, design houses, test equipment suppliers, and package and testing houses partner to develop cost-effective test mythologies and strategies.

Victor Peng, SVP at Xilinx, updated the audience on their ongoing commercialization of Xilinx 7V2000T FPGA with their "stacked silicon interconnect technology" (SSIT).The company's FPGA 28nm slices are assembled "side by side" on a silicon interposer with 65nm interconnect wiring. They found the interposer was an excellent way to handle the 28nm chip low-k fragility. Chip fabrication, interposer fabrication and bumping is being done by TSMC. Chip bumping and module assembly is being done by Amkor.

Peng reports that Xilinx is on schedule for sampling in calendar year 2011. Peng also noted that the company "believes in full 3D IC stacking (no interposer)" but that it will take a little longer for that technology to become standardized in the infrastructure.

Solid State Technology | Volume 54 | Issue 10 | November 2011

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