Litho tool explores tradeoffs at 20nm and below

11/01/2011

At the SPIE BACUS Photomask Technology conference (Sept. 19-22, Monterey, CA), D2S announced a mask-wafer double simulation accelerated workstation for R&D exploration, bit-cell design, hot-spot analysis, and mask defect categorization for qualifying and optimizing semiconductor designs at the 20nm node and below. TrueMask DS enables the efficient exploration of the various trade-offs: complex optical proximity correction (OPC), inverse lithography technology (ILT), source mask optimization (SMO), and the cost and turnaround time of masks for critical circuits.

"It's an exploration platform that allows designers to explore shapes that can be efficiently written on mask writers and is also best for wafer yield," said Aki Fujimura, CEO of D2S (and managing company sponsor of the eBeam Initiative). "In 20nm and below nodes, unlike previous nodes, mask shapes, mask write times, and wafer yields are becoming trade-offs against each other." The new platform allows exploration of the trade-offs.

Independent validation of mask-wafer double simulation approach. In this example, the D2S MB-MDP of ILT mask shapes is the best choice for better wafer quality (lower PV band) and faster mask write time (lower shot count). Courtesy GlobalFoundries, BACUS 2011 paper #8166-110, Gek Soon Chua, et al.

Fujimura explained how accuracy inherent in mask writers is impacted at 20nm and below. "For mask writing, which is based on 50keV e-beams, discontinuity occurs below 80nm sizes," he said. Above 80nm mask dimensions, one could count on the shot size being faithfully reproduced on the mask surface, he noted; going below 80nm, however, one is no longer is able to get the same shape nor will the size be reproduced every time, nor will the printed feature be reliable in size. Therefore, the "bundled model" lithography simulation methodology the industry has been using for over 10 years "is no longer enough," he asserted. By using a separated mask model instead of the typical bundled model, the new workstation modeling includes the mask effects. An independent validation of the mask-wafer double simulation approach is shown in the table above.

The platform also is important for cost reduction, Fujimura noted. A typical cycle for doing mask simulation followed by lithography simulation might be hours of work. Because the new system uses a graphics processing unit (GPU) accelerator, the amount of work will be reduced to tens of seconds. Being able to get the feedback on the impact of changing mask shapes in such a short period of time enables substantial time savings on the trade-off evaluation.

Other features of the platform include: 0.1nm resolution mask simulation up to 300 ?? 300??m (mask dimensions), including overlapping shots and dose modulation; advanced e-beam modeling with arbitrary point spread functions for exploration; interactive aerial litho simulation from hardware acceleration; 5 ?? 5??m (on wafer) interactive mask-wafer double simulation; and SEM interface for overlay analysis of pictures with simulations. ??? D.V.

Solid State Technology | Volume 54 | Issue 10 | November 2011

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