Issue



Package-on-package: thinner, faster, denser


07/12/2011







Executive Overview


Package-on-package (PoP) has been an enabling technology for the integration of more features and functions in smart mobile devices. Because of the significant technical, business and logistics benefits package stacks provide, system designers are applying PoP to a wider range of new applications and are demanding new PoP component advancements from their supply chains. Recently, two new interconnect technologies have emerged that are delivering the higher densities that next-generation PoP applications require. through mold via (TMV), and fine pitch FC with copper pillar bumps.


Lee Smith, Amkor Technology, Chandler, AZ USA


PoP is used in a range of applications for the 3D integration of signal processing and system memory components driven by the mega trends of mobility, multimedia and connectivity. Of particular note (which will be the focus of this article) are cell phone through smartphone and media tablets, as these applications drive PoP adoption at higher ??? processor/memory speeds, silicon and interconnect densities in thinner stack ups. TechSearch International reports 390 million PoP units shipped last year, which represents over a 70% CAGR from the 25 million first generation PoPs shipped in 2005 when Nokia was the primary adopter following its collaboration work in the development and productization of PoP [1]. With an average of one PoP stack per device, the five year growth forecast is closely tied to the overall smartphone and tablet markets.


First-generation PoP


The first-generation of PoP can be characterized as: wirebond interconnects for the mobile processor fabricated on 130 to 90nm CMOS running both the base band modem and multimedia application processing functions. A 0.65mm pitch memory interface density was applied to allow stacking clearance over the center pin gate molded bottom package with 0.5mm pitch BGA density to the mother board. Overall, PoP stack heights varied from 1.4 to 1.8mm based on the number of memory die [2-4] stacked in the top package with 12x12 and 14x14mm -- the highest volume PoP body sizes. These PoPs provided 128 to 152 pin memory interfaces supporting combo memory architectures up to SDRAM speeds of 133MHz, typically with NOR flash for the modem codec. Phone board assembly lines developed and optimized their surface mount technology (SMT) processes for one pass reflow stacking, which provides lowest total cost of ownership with maximum supply chain flexibility. Two- pass reflow SMT pre-stacking was used primarily for engineering sampling and early risk production while one-pass reflow stacking lines were being qualified or stabilized.


In 2007, the leading edge for PoP were dedicated application processors at 65nm CMOS in a bare die flip chip (FC) bottom PoP configuration with higher density 0.5mm memory interfaces and 0.4mm bottom BGA pitches. This density required thinning the FC silicon wafers to 100??m and ensuring care in handling the component through package assembly, test and surface mount stacking to avoid die crack and edge chip out defects. Low power DDR speeds up to 167MHz were supported in PoP stacks compressed to 1.2 to 1.5mm thick. In 2009, 45nm high speed application processors were emerging in PoPs running up to 1GHz clock speed in this same FC bare die PoP configuration with LP DDR up to 200MHz. Figure 1 illustrates the first generation PoP stack configurations and attributes.










Figure 1. First-generation PoP stacks.

At this time, two-pass reflow pre-stacking emerged in high volumes to support the more challenging, thin, high-density FC PoP stacks and the shorter product life cycles in the dynamic smartphone market. Thinner/higher density FC PoP stacks presented greater warpage control challenges because of the wider CTE mismatch of the bare silicon die to organic substrate and finer pitch BGA interfaces. These technical challenges were exacerbated by shorter product life cycles and the emergence of less experienced phone board assembly lines in China, pressed to produce higher daily outputs. Since pre-stacking increases floor space, equipment, processing and cycle time costs in the supply chain with greatly reduced sourcing flexibility, it is not seen as a viable approach for the overall industry, so significant work continued in SMT stacking processes.










Figure 2. The construction and package stack-up for the TMV PoP test vehicle for the joint study with Sony Ericsson.

As I summarized in 2008 [2], smartphone roadmaps demanded higher speed/density signal processor and memory architectures in smaller/thinner stacks that were projected to exceed the capability of the first generation of PoP technologies. It was becoming increasingly clear to the industry that a next-generation PoP technology platform was required to break through the density and flatness challenges associated with the first generation of PoP technologies to enable higher density 3D integration. As a result, a number of smartphone and mobile processor suppliers began joint projects for the evaluation and qualification of Amkor's next-generation PoP with through-mold via (TMV) technology which was disclosed at ECTC earlier in the year [3]. Of note was the joint paper at SMTA International with Sony Ericsson Mobile Communications [4] where a five net high density TMV PoP test vehicle (Fig. 2) was designed to characterize the SMT and board level reliability performance against the baseline first generation FC PoP technology. This TMV PoP test vehicle was further characterized in a joint project with Celestica as reported at SMTAI the following year [5]. In addition, a 12x12mm four net test vehicle was designed and evaluated in a three way project with Amkor, ST Microelectronics and Nokia as reported in the summer of 2009 [6].


PoP now


Last year, high-density, next-generation PoP represented just over a quarter of Amkor's PoP volumes, whereas this year, the TMV technology is forecasted to exceed 80% of our PoP business due to the higher device speeds and package densities of today's PoP stacks. The standard two-row memory interfaces at 0.5mm pitch (described in the previous joint papers) are now complemented by designs with a three-row interface at 0.5mm pitch and a two-row interface at 0.4mm pitch. The driver for these higher density interfaces has been the higher speed and wider bus required by low power DDR2 running to 400MHz. A 0.4mm bottom BGA pitch has become the dominant PoP to motherboard interconnect density, and smaller PoP body sizes have emerged including rectangular sizes that can provide challenges for SMT stacking, but may provide form factor flexibility for system designers.


With the rapidly expanding demand for thinner smart mobile devices, PoP ceilings from 1.0 to 1.4mm height are in high demand, requiring reduction of all layers and interfaces in a PoP stack. To enable this, a new flip chip technology was required that provides substrate, bump stand-off and silicon thickness reductions. At ECTC 2009, Amkor disclosed a copper pillar bump, fine-pitch flip chip technology that is proving to be a breakthrough technology [7]. Below is a list of the key cost/performance benefits that qualify this as a breakthrough technology as described by TI in a joint press release with Amkor [8]:



  • Enables FC wafer/die thinning to 60??m with a roadmap to 40??m;

  • Reduces bump stand-off and underfill fillet / bleed out dimensions;

  • Enables substrate layer count and core thickness reduction while enabling higher I/O density and improved design flexibility for signal and power integrity;

  • Enables probe before bump and elimination of final metal bump array redistribution layer or costly passivation layers, typically required with solder FC; and

  • Overall - enables smaller, thinner and lower cost high density bottom PoPs.










Figure 3a. Fine-pitch FC, copper pillars with lead-free solder cap (photos).

Significant collaboration and investment were key in developing and deploying fine-pitch FC copper pillar bumping and assembly technologies, as summarized at ECTC 2011 in a joint paper between Amkor and TI [9] (Fig. 3). Fine-pitch FC, combined with through-mold via stacking interconnects promises to deliver a scalable platform for PoP advancements for years to come.










Figure 3b: Fine-pitch FC, copper pillars with lead-free solder cap (illustration).

The future of PoP


The demand for mobility, multimedia and connectivity is expanding across many different electronic systems, thereby driving a new era of applications being termed ???smart products or smart devices.' In-Stat is forecasting mobile processors will expand to nearly 4 billion units by 2014 with the following quote extracted from its April 8, 2011 Market Alerts. "Mobility and mobile devices are reshaping the entire high-tech industry. Everything from silicon chipsets to software to services are being reshaped by mobility. Smartphones will continue to be the innovation driver in mobile processor technology, particularly with the integration of multiple cores, GPUs and baseband modems. While there will be some convergence of devices and usage models, consumer patterns and the history of the high-tech market indicate that the total number of mobile devices will continue to expand, increasing the TAM of mobile processors to nearly 4 billion by 2014, says In-Stat (www.in-stat.com)."


As a result, PoP adoption is expanding to a wider range of applications requiring more system and IC designers to integrate PoP into their product designs without the benefit of past experience in PoP implementation. Design and development timelines continue to reduce, while design challenges are quickly escalating, making this a daunting task for even experienced PoP design engineers. A word of advice (based on my experience in driving the design, development and deployment of the first generation PoP technology from concept to production in just 15 months): collaborate across your design through supply chains ??? leverage the expertise available to you with open, continuous communication based on sound data sharing and analysis without the barrier of "not invented here" constraints!


Mobile processor speeds are trending to 2GHz at the 28nm node in multi-core architectures with advanced graphics processing capabilities. On the memory side, low-power DDR3 is in development, projecting maximum DRAM frequency over 1GHz. At these high data rates, signal/power integrity and thermal challenges will require that the IC and package designers team together on new designs. This teaming begins from the architecture and die floor planning stage, all the way through device qualification to ensure the cost/performance benefits PoP has delivered, to extend to third-generation challenges. These challenges will likely include:



  • Higher density memory interfaces driving the development of 0.3mm pitch stacked interconnects. Fine-pitch stacked interfaces can provide size reduction, as well as enable new memory architectures, and provide electrical performance benefits for higher speed requirements.

  • The integration of high density die stacks in the bottom package, using FC + wirebond and FC die stacks with through-silicon via interconnects to enable integration or reuse of advanced modem and application processing chips.

  • The integration of decoupling capacitors for high-speed signal conditioning, both as discrete SMT and substrate embedded structures.

  • The development of thin thermal management technologies.

  • Continuous reduction in die and material thicknesses to provide high density PoP stacks below 1.0mm height ceilings.


Conclusion


Amkor has committed significant resources over the last decade to develop and deploy PoP technologies, with strong roadmaps to provide the continuous cost/performance advancements system and IC designers are demanding. The combination of TMV and fine pitch FC copper pillar technology platforms will enable PoP to provide the 3D integration benefits third-generation mobile processors will require for broad adoption in smart devices.


References:



  1. L. Smith, "Package-on-Package: The Story Behind this Industry Hit," Semiconductor International, June 2007.

  2. L. Smith, "Driven by Smartphones, Package-on-Package Adoption and Technology are Ready to Soar," Chip Scale Review, July 2008.

  3. J. Kim et al, "Application of Through Mold Via (TMV) as PoP Base Package," 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, May 27-30, 2008.

  4. C. Zwenger, et al., "Surface Mount Assembly and Board Level Reliability for High Density PoP Utilizing Through Mold Via Interconnect Technology," SMTA International Conference, Orlando, FL, Aug. 17-21, 2008.

  5. H. McCormick, et al., "Assembly and Reliability Assessment of Fine Pitch TMV PoP Components," SMTA International Conference, San Diego, CA, Oct. 4-8, 2009.

  6. M. Dreiza, et al., "Joint Project for Mechanical Qualification of Next Generation High Density PoP with Through Mold Via Technology," 17th European Microelectronics & Packaging Conference, Rimini, Italy, June 16, 2009.

  7. M. Lee, et al., "Study of Interconnection Process for Fine Pitch Flip Chip," 59th Electronic Components and Technology Conference (ECTC), San Diego, CA, May 26-29, 2009.

  8. Press Release, July 7, 2010, Amkor Technology and Texas Instruments Deliver Industry's First Fine Pitch Copper Pillar Flip Chip Packages to Market.

  9. C. Zwenger, et al., "Next Generation Fine Pitch Cu Pillar Technology ??? Enabling Next Generation Silicon Nodes," 61st ECTC, Lake Buena Vista, FL, May 31-June 3, 2011.


Biography


Lee Smith received his BS with honors from the U. of Wisconsin, Stout, and is VP, Marketing & Business Development, at Amkor Technology, Inc., 1900 S. Price Rd., Chandler, AZ 85286 USA


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