Focus on 3D TEST at IEEE Workshop

01/01/2011

The first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits "3D-TEST," held in Nov. in Austin, TX, was the latest example of how the 3D topic is being picked up by the test community. "At the ITC last year coverage of 3D testing was limited. This year we see significant coverage in the main ITC meeting, followed by a this workshop dedicated to 3D Test issues which was attended by nearly 100 professionals," said Erik Jan Marinissen of IMEC, one of the event chairs.

Marinissen presented the early results of the IEEE Computer Societies standardization study group on 3D Test. The 42 corporate and institute participants include: AMD, ARM, Cadence, Cascade Microtech, Cisco, IBM, IMEC, Infineon, ITRI, Mentor Graphics, Qualcomm, ST Micro, Synopsys, TI, TSMC and Verigy. Standardization needs were identified; see table above.

Bob Patti, CTO of Tezzaron, discussed their form of built-in self-test (BIST), called Bi-STAR. He claims that Bi-STAR tests and compares 2304 bits/clock cycle, "more than 100× faster than can be achieved by any external memory tester." Reportedly Bi-STAR can test and repair bad memory cells, line drivers, and sense amps; shorted word lines and bitlines; leaky bits; and bad secondary bus drivers.

Sanjiv Taneja, VP for front-end design at Cadence, showed a long list of test challenges. Integration of design and test, he said, is the only way to solve these complex issues, and concurrent optimization for area, timing, power, and testability is the only means to achieve required predictability.

Ken Smith of Cascade Microtech showed details on their high-density MEMS probe card technology, which makes 1g tip forces feasible and very low pad damage (and scrub marks <100nm deep) possible at 40µm array pitch.

Such lithographically fabricated probe cards "enable scalability which will lower cost just as IC linewidth scaling has reduced the cost of IC functions," Smith said. "Instead of probe costs being roughly proportional to pincount, the cost of a MEMS probe should be roughly proportional to the probe area."

SEM of probe tip array. Tips are 5µm square and 20µm tall.

Chen Hao, test engineer at TSMC, presented an assessment of the failure modes seen when fabricating 3D ICs with microbumps including issues with alignment, TSV voids, impurities at the bonding interfaces, nonuniformity in the insulation liner, and TSV delamination from the substrate due to the thermal stress and warpage.

Besides testing, thermal issues, electromigration, TSV redundancy, and ESD also need attention, he added. — Dr Phil Garrou, contributing editor

Read Phil Garrou's blog at  www.apmag.com.

More Solid State Technology Current Issue Articles
More Solid State Technology Archives Issue Articles