Identifying root causes of systemic yield loss using model-based yield analysis
07/01/2009
An Carlson, Rudolph Technologies, Inc., Flanders, NJ USA
In modern semiconductor fabs, final yield can be affected by many factors. From bare wafer to final packaging, hundreds of process steps are involved, and each process or tool can have an impact on final yield. Statistical process control (SPC) has been used extensively for monitoring process health and identifying out-of-control parameters. This article contrasts the limitations inherent in SPC with the benefits of using model-based yield analysis software and provides an example of these benefits based upon a case study using production data from a process line at a major memory manufacturer.
Due to the complex nature of modern processes, process deviations have different yield impacts. Even processes within traditional SPC control limits can negatively affect yields due to interactions between different process aspects. In such cases, determining the root cause of the yield loss using SPC alone is difficult and time-consuming. Model-based yield analysis software provides a quick and effective means of root cause analysis [1].
This approach, which builds models relating in-process inspection and metrology data to final yield and wafer acceptance test (WAT) results, helps engineers to identify the yield limiting factors caused by variations in production processes. The technique identifies critical process steps, as well as yield-limiting process tools, and lists possible root causes ordered by their likely impact on yield.
It is possible to separate the significant systematic problems from process deviations with negligible impact because both deviation from the process target and the impact to yield are considered in the analysis. As a result, engineers are able to find and resolve process problems that may be difficult to discern with SPC and other yield analysis tools, in a fraction of the time required for similar manual analysis.
Limitations of statistical process control
SPC uses statistical techniques to measure and analyze the variations that occur within a manufacturing process as a means of minimizing yield loss. Using metrology measurements, a target value, as well as upper and lower acceptable deviations from that target are established. The ability of a process to remain within these specification limits is referred to as process capability (Cp/Cpk). This measurement is used to determine the stability of a process, with a higher Cp/Cpk indicating a more stable process. A low Cp/Cpk number typically indicates a problem with the process.
Having determined that one process is more stable than another does not, however, tell whether a particular metrology process is actually having a more significant negative impact on yield than another. For example, a given metrology (call it Metrology 2) can have two excessive target deviations, one above the upper limit and one below the lower limit. Whereas a third metrology (Metrology 3), by contrast, has only one target deviation above the upper limit.
While such measurements highlight the stability of a process, in the event of a yield excursion, the SPC approach requires experienced fab engineers to engage in a time-consuming manual evaluation process. First, the critical process steps and their Cp/Cpk values must be identified. This analysis may yield a long list of probable root cause candidates. Each of these candidate process steps must then be individually analyzed down to the equipment level to determine the root cause — an exercise that typically takes several hours, and during which, the process line sits idle.
Model-based low yield analysis
Model-based low yield analysis software is designed to address this very weakness in the SPC approach. It analyzes the sensitivity of process yields to variations in Cp/Cpk occurring at different steps in the process, based on a predictive model using a fab’s historical data relating inline metrology measurements to final yield. Establishing the initial model requires a relatively small amount of data, facilitating quick system set up. The software then adapts and improves the model as more data becomes available.
 Figure 1. Low yield spider chart. |
When an excursion occurs, the software, in a matter of minutes, analyzes the data to provide a probability-ordered list of possible root causes. The software arrives at this ordered list by calculating a root cause score for each low yield wafer. Both the deviation from the process target and the impact on yield are considered in assigning this score. This data can be displayed in either a table or via a low-yield spider chart (Fig. 1). This chart highlights two probable root causes: trench depth or overlay issues. The distances of the dots from the center on the spider legs indicate the probability ordering of these root cause candidates.
 Figure 2. Sensitivity analysis. |
The key to this approach is the model’s ability to correlate different process changes with yield to determine which have a greater impact. For example, as Fig. 2 shows, yield was much more sensitive to variations in the process measured by Metrology 3 than those for Metrology 2.
Low-yield analysis case study
The case study used two weeks of production data from two similar devices produced in a major memory manufacturer’s fab. A total of 60 wafers with merged yield were included in the study. The model used was a subset of a larger scale yield model. The dataset contained wafer-in-process (WIP), sort and inline metrology data and included 11,482 inline measurements and 98 quality measurements.
 Figure 3. Low yield analysis on lot AAm217. |
The wafer lots were examined using Rudolph’s yield management system. Wafer lots with <80% yield were considered to be low yielding. One lot was found to contain seven wafers that had below the minimum percentage yield. Low yield analysis on this lot identified two parameters as likely root cause candidates. Figure 3 shows that deviations in both these parameters resulted in significant and precipitous drops in yield.
 Figure 4. Cpk analysis results. |
A traditional SPC approach was also used to examine the data. A Cpk analysis highlighted 19 possible root cause candidates for the yield excursion. Both parameters illustrated in Fig. 3 were among the 19 candidates listed (Fig. 4), confirming the results of the model-based yield analysis. The difference, however, is that a fab engineer using only SPC techniques would have had to examine 19 potential root causes versus the two identified via model-based yield analysis. The model-based approach can also automatically track the root cause to the equipment level.
This study demonstrates the advantages model-based yield analysis offers over manual SPC techniques. In a matter of minutes, the two most likely causes from among the 19 potential candidates were identified, and the specific process equipment responsible for the yield excursion was determined. A similar manual analysis would typically require hours to reach the same conclusion. The fact that both approaches ultimately reach the same conclusion supports the validity of model-based yield analysis.
Conclusion
In today’s fabs, there are hundred of process steps that can significantly impact final yield. SPC has been used extensively to monitor process health and identify out-of-control parameters. SPC alone, however, cannot perform the analysis required to determine which parameter is the root cause of a particular yield excursion. This, traditionally, has required a time-consuming manual effort by experienced fab engineers. By automatically deriving correlations between variability in multiple process parameters and process yield, model-based analysis dramatically reduces the time required to determine the root causes of yield losses, resulting ultimately in faster recovery from yield excursions and higher overall process yields.
References
- William Martin, et al., “Identifying Root Cause of Systemic Yield Loss Using Model-based Yield Analysis,” AEC/APC 2008.
An Carlson received her BS degree in engineering from Shanghai Jiao Tong U., and her PhD from Massachusetts Institute of Technology. She is an applications engineer at Rudolph Technologies, Inc., One Rudolph Road, P.O. Box 1000, Flanders, NJ 07836 USA; ph. 952-259-1647; [email protected].