Issue

Robert de Neve, E Systems Technology, Mountain View, CA USA

Since Intel's Bohr published his seminal paper on interconnect scaling in 1995, the IC community has been searching for a manufacturable low-k dielectric which could scale to below k=2.0.

Researchers from the IBM Alliance have developed a new germanium ion implantation process that implants Ge into the shallow silicon channel region prior to high-k/metal gate (HKMG) stack depositions.

Also presenting at next month's IEDM, Intel and Micron researchers will reveal the key process advances and electrical results behind their multilevel cell (MLC) 64Gb NAND flash memory technology.

At the Annual SPIE/BACUS Symposium 2010 (Sept. 13-16), the eBeam Initiative had several members jointly presenting the latest achievements related to an design for e-beam (DFEB) manufacturing approach, showing the effectiveness of DFEB mask technology on advanced photomasks at the 22nm node and beyond.

About 40 fellow techno-geeks attended a Sept. 15 meeting of the NCCAVS CMP Users Group at SEMI headquarters in San Jose, CA, with an agenda comprising seven topics for a combination of technical, technical marketing, and marketing presentations, all with the theme of chemical mechanical planarization (CMP) for the hard-disk drive (HDD) industry.

At DISKCON 2010 (Sept. 9-10, Santa Clara, CA), Toshiba Corp. presented details behind its use of bit-patterned media (BPM) to fabricate a hard disk with an areal density of 2.5TB/in2 and a practical servo pattern.

Researchers at Rice U. say that a new switching memory they built with electrically manipulated 10nm graphite strips doesn't actually need the graphite???good ol' reliable silicon oxide will do just fine.

The needs of replacement metal gate HKMG process flows for 45nm node and below CMOS manufacturing are now being met with processes using consumables designed specifically for these steps. Paul Feeney, CMP Fellow, Cabot Microelectronics Corp., Aurora, Illinois, USA

Cost-of-ownership (COO) will be a main driver for ALD equipment selection in cost-sensitive markets; and in foundry or other logic applications, equipment choice is more a mix between COO, turn-around time and process performance considerations. M. Verghese, ASM, Phoenix, AZ USA; J. W. Maes, ASM, Leuven, Belgium; N. Kobayashi, ASM, Tokyo, Japan

New polymers that are capable of buffering die structures from the package stresses will be required of advanced packaging; and materials will continue to evolve to meet the new requirements. Toshiaki Itabashi, DuPont Semiconductor Fabrication Materials, Kanagawa, Japan

FDSOI technology exhibits outstanding variability results, thanks to the use of an undoped channel, and to the good control of silicon film thickness already reached today on commercial SOI wafers. F. Andrieu, O. Weber, J. Mazurier, O. Faynot, CEA-Leti, Grenoble, France