Issue

It’s springtime for engineers in electronics, computing, and chip architecture.

Worldwide semiconductor capacity and output both slowed significantly in 4Q07, but for the first time in a year and a half factory utilization rates crept up above the benchmark 90% level.

Extending Moore’s Law to 22nm and beyond for logic circuits calls for new concepts in manufacturing processes and device architectures.

There’s much more going on at the Belgian research center IMEC than the relentless pursuit of Moore’s Law and semiconductor process technology scaling.

In 2003, NXP CAEN opened a new pilot line dedicated to innovative solutions in system-in-a-package (SIP) on 150mm wafers.

The Tachyon 2.5 computational lithography platform and the Tachyon DPT, an advanced double patterning technology (DPT) solution, have been introduced.

System improvements to the model 9200 PanelPrinter system include handling as many as 60 reticles on its automated reticle library subsystem, with automatic loading of up to 6 masks/layer.

CMP is rapidly becoming one of the most important and widespread fab processes enabling the continuation of device shrinks.

In low k1 lithography, process integration and qualification are of little value without OPC-corrected masks.

The optimization of wet clean and surface preparation processes is an industry challenge, due in part to the lack of adequate inspection techniques to detect nonvisual defects (NVD).

At previous technology nodes, scanner systematic signatures–including illuminator pupil-fill and polarization, lens aberration, lens apodization, and flare–could be ignored without significantly impacting optical proximity compensation (OPC) accuracy.

Short range proximity effects in maskmaking processes require compensation over and above that presently applied to account for other effects such as electron backscattering.

Advances in traditional CMOS scaling techniques are reaching their limits, bringing up the need for new materials and novel device designs.

Developers of flexible, printed, and organic electronics (FPOE) products face significant challenges in scaling to true volume production.