Issue

It’s easy to think of the semiconductor industry as an anomaly in the history of business because, in fact, it is.

Replacing traditional TFT-LCD manufacturing with a lower-cost alternative that is also a more efficient technology is (forgive the pun) a bright idea that should be attractive to manufacturers.

Multiple semiconductor and related processes-including diffusion, RTP, ALD, etch, and DUV lithography-currently use water vapor as part of manufacturing.

The overall utilization efficiency of production ion implanters is strongly influenced by the build up of solid deposits inside the vacuum system.

Applying foundries’ recommended design rules can often raise design costs because many recommended design rules result in trade-offs, requiring designers to spend more time in verification.

This month, SST presents a preview of the March edition of Chip Forensics, an SST online column by Dick James, senior technology adviser at Chipworks, a specialty reverse engineering company that takes apart ICs and electronics systems in order to provide engineering information for its customers.

Driven by the needs for mobile personal electronics, wafer-level packaging (WLP) is now being used for many mainstream ICs.

Traditionally, MEMS devices have been developed using a combination of custom design and manufacturing techniques in a select number of captive MEMS foundries or in one of the commercial specialty MEMS fabs that have sprung up in recent years.

Continuous evolution marks the electronics industry’s progress toward even thinner, lighter and more flexible products.

A flat panel deposition technology, which utilizes a rotary target arrangement instead of the traditional planar and is also applicable beyond Gen 8.5, is described. In addition to enabling manufacturing and materials cost reductions in pre-sputter qualification, target consumption is reduced and data is presented showing that thickness uniformity, sheet resistivity, and target erosion profiles comply with Gen 8.5 TFT requirements.

In general, emerging materials will augment silicon transistor technology by providing enhanced speed, lower-power consumption, improved heat dissipation, improved memory capacity/data retention, or added RF/analog functionality while maintaining the large scale integration capability of CMOS.

Multiple-gate FETs incorporating narrow silicon fins have been investigated as an alternate to traditional CMOS technology.

Processes have been developed to create n-type silicon cells on thin wafers with screen printed aluminum-alloyed rear junctions.

Just as MEMS developers are waking up to the fact that metrology tools can add value to development and fabrication of MEMS devices, tool suppliers are facing the challenges-and opportunities-of serving an increasingly complex market.