Issue

The limits of traditional CMOS scaling are at hand, combined with an unprecedented financial crisis in the electronics industry.

2008 was a big game of “chicken” in the DRAM sector, as firms floored their investment and output pedals in 2008 hoping competitors would give up first.

Chipmakers are trying many paths toward high–k metal gate dielectric (HK+MG) CMOS for 32nm and beyond.

Researchers at the National Institute of Standards and Technology (NIST) have updated a well–known technique for measuring material properties to gauge the mechanical strength of low–k films, to help devicemakers better identify interconnect dielectric film candidates.

The solar industry’s recent growth spurt has shown that success brings new challenges.

The Discover Solar software package is a reengineered version of the company’s inline defect analysis and data management system to target high–volume photovoltaic production, offering automated process control and the ability to perform root cause analysis closer to real time.

What is the most viable path to enabling the design shrink to 22nm? Will a solution emerge that overcomes the technical and economic hurdles currently being anticipated in both manufacturing and design?

The most aggressive IC manufacturers target EUVL pilot line introduction in 2011.

A new F₂ gas mixture was evaluated as a substitute for conventional cleaning gases such as, NF₃, C₂F₆, and CF₄, in a CVD chamber. The new mixture was compatible with the equipment used and improvement was seen in the etch rate as well as a reduction in the amount of gas needed to complete the clean.

The extensive utilization of strain engineering in the semiconductor industry led to the subsequent development and refinement of a variety of analytical techniques that helped to improve manufacturing control of stress level in thin film, as well as to measure strain on individual devices.