Issue



Table of Contents

Solid State Technology

Year 2006
Issue 7

DEPARTMENTS

Editorial


Here comes the sun

Over the past 30 years, the solar industry has made a number of false starts, and the underlying photovoltaics (PV) technology has gained a reputation for being impractical without government subsidies.


World News


World News

Membership in the elite group of chipmakers spending at least $1 billion will expand to 16 companies this year, with memory firms particularly aggressive in their capacity investments, according to IC Insights Inc.


Tech News


“Bulking up” with direct silicon bonding

Layer-transfer technology is becoming more important as the demand for high-performance applications requiring enhanced semiconductor functions increases, and other applications such as MEMS and packaging continue to expand.


Software


The Open Modeling Coalition creates a new effective current source model

New models are needed to account for the process variations in nanometer-era silicon manufacturing, so that new chips can be designed with acceptable yield and performance without requiring costly re-spins.


Industry Forum


Containing wafer costs while customizing CMOS

In the late 1980s and early 1990s, CMOS became increasingly standardized as dimensions shrunk from 1µm to 0.


SPECIAL-REPORT

Gate Stack Engineering


Targeting 45nm with improved SiON films and extended gate dielectrics

Silicon oxynitride gate-stack dielectrics are reaching limits for use beyond 65nm technology.


Gate Stack Engineering


Optimizing gate dielectrics using laser-spike annealing

For the past several years, the need for advanced gate-stack materials has been listed by Sematech as one of the top technical challenges faced by the semiconductor industry [1].


FEATURES

Interconnects


Combining seed layers enables the use of HAR copper interconnects

The lower resistivity of copper vs. aluminum facilitates denser and faster ULSI devices with on-chip copper interconnects.


Metrology


An alternative dopant-measurement method for analyzing ULE implant

This article describes an alternative dose-measurement method of analyzing ultra-low energy (ULE) ion implantation.


Resists


Evaluating topcoat options for immersion litho resists

Three resist systems are commonly available for 193nm immersion lithography: resist with solvent-soluble topcoat, resist with an aqueous developer-soluble topcoat, and special 193i immersion resist needing no topcoat at all.


Auto Cd Sem Edge Placeme


Auto CD-SEM edge-placement error for OPC and process modeling

OPC models for leading-edge lithography must be calibrated with empirical data, and the measure of mismatch between design-intent and CD-SEM data is termed edge-placement error (EPE).


Fab Management


Searching for greater fab productivity with 300mm Prime

The ability to improve IC manufacturing costs has been one of the great success stories of the semiconductor industry.


PRODUCTS

Product News.html


Product News

The Cougar-SMT X-ray inspection system can image components in 2D and 3D for thorough inspection of applications requiring high magnifications, such as MEMS/MOEMS, semiconductor packages, and high-density interconnects.